| 1 | adapter_khz 1000 |
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| 2 | |
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| 3 | reset_config trst_and_srst separate |
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| 4 | # c100 config. |
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| 5 | # This is ARM1136 dual core |
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| 6 | # this script only configures one core (that is used to run Linux) |
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| 7 | |
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| 8 | # assume no PLL lock, start slowly |
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| 9 | set _CHIPNAME arm |
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| 10 | set _ENDIAN little |
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| 11 | #set _CPUTAPID 0x0f67e8ef |
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| 12 | set _CPUTAPID 0x07b37477 |
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| 13 | |
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| 14 | # Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register |
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| 15 | jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID |
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| 16 | jtag newtap $_CHIPNAME cpu1 -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID |
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| 17 | # MSP430FR5857 |
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| 18 | jtag newtap msp gsc -irlen 8 -ircapture 0x91 -irmask 0xff |
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| 19 | |
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| 20 | set _TARGETNAME $_CHIPNAME.cpu |
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| 21 | set _TARGETNAME1 $_CHIPNAME.cpu1 |
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| 22 | target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME -variant "ARM11 MPCore" |
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| 23 | target create $_TARGETNAME1 arm11 -endian $_ENDIAN -chain-position $_TARGETNAME1 -variant "ARM11 MPCore" |
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| 24 | |
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| 25 | # C100's ARAM 64k SRAM |
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| 26 | #$_TARGETNAME configure -event reset-init { cns3xxx_init } |
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| 27 | $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x10000 -work-area-backup 0 |
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| 28 | |
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| 29 | flash bank test cfi 0x10000000 0x1000000 2 2 arm.cpu |
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| 30 | |
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| 31 | proc fwd {n} { |
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| 32 | for {set i 0} {$i < n} {set i [expr $i+1]} { |
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| 33 | step |
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| 34 | } |
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| 35 | } |
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| 36 | |
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| 37 | proc cns3xxx_init {} { |
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| 38 | reset |
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| 39 | halt |
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| 40 | targets 1 |
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| 41 | halt |
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| 42 | targets 0 |
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| 43 | mww 0x72000400 0x0 |
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| 44 | mww 0x72000408 0x1410 |
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| 45 | mww 0x7200040C 0x6 |
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| 46 | mww 0x72000410 0x0 |
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| 47 | mww 0x72000414 0x0 |
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| 48 | mww 0x72000418 0x0 |
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| 49 | mww 0x7200041c 0x0 |
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| 50 | mww 0x72000420 0x0 |
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| 51 | mww 0x72000424 0x18 |
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| 52 | mww 0x72000404 0x1 |
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| 53 | mww 0x72000404 0x3 |
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| 54 | |
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| 55 | mww 0x72000428 0x6e550 |
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| 56 | mww 0x72000428 0x6e551 |
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| 57 | |
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| 58 | sleep 10 |
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| 59 | |
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| 60 | mww 0x72000428 0x6e550 |
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| 61 | mww 0x72000428 0x6e552 |
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| 62 | mww 0x72000428 0x6e550 |
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| 63 | mww 0x72000428 0x7e550 |
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| 64 | mww 0x72000430 0x2 |
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| 65 | #CAS Latency |
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| 66 | mww 0x72000014 0xc |
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| 67 | |
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| 68 | mww 0x7200004c 0x44 |
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| 69 | |
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| 70 | mww 0x7200001c 0x2 |
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| 71 | |
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| 72 | mww 0x72000020 0x12 |
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| 73 | mww 0x72000024 0x18 |
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| 74 | mww 0x72000028 0x406 |
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| 75 | mww 0x7200002c 0x4d4f |
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| 76 | mww 0x72000030 0x406 |
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| 77 | mww 0x72000034 0x4 |
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| 78 | mww 0x72000038 0x6 |
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| 79 | mww 0x7200003c 0x3 |
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| 80 | mww 0x72000054 0x1220 |
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| 81 | |
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| 82 | mww 0x72000040 0x3 |
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| 83 | mww 0x72000044 0xc8 |
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| 84 | mww 0x72000048 0xc8 |
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| 85 | |
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| 86 | mww 0x7200000c 0x14012 |
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| 87 | mww 0x72000010 0x618 |
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| 88 | mww 0x72000200 0xff |
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| 89 | mww 0x72000008 0xc0000 |
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| 90 | mww 0x72000008 0x0 |
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| 91 | mww 0x72000008 0xa0000 |
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| 92 | mww 0x72000008 0xb0000 |
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| 93 | mww 0x72000008 0x90004 |
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| 94 | mww 0x72000008 0x80b62 |
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| 95 | mww 0x72000008 0x0 |
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| 96 | mww 0x72000008 0x40000 |
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| 97 | mww 0x72000008 0x40000 |
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| 98 | mww 0x72000008 0x80a62 |
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| 99 | mww 0x72000008 0x90384 |
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| 100 | mww 0x72000008 0x90004 |
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| 101 | mww 0x72000004 0x0 |
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| 102 | |
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| 103 | flash probe 0 |
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| 104 | flash write_image u-boot.bin 0x60000000 |
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| 105 | } |
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| 106 | |
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| 107 | # Function sets MSP430FR5857 into JTAG4 and resets this board |
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| 108 | proc init_reset {mode} { |
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| 109 | echo "default" |
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| 110 | jtag_reset 0 0 |
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| 111 | |
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| 112 | echo "srst low" |
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| 113 | jtag_reset 0 1 |
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| 114 | sleep 500 |
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| 115 | |
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| 116 | echo "srst high" |
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| 117 | jtag_reset 0 0 |
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| 118 | sleep 1 |
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| 119 | |
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| 120 | echo "srst low" |
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| 121 | jtag_reset 0 1 |
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| 122 | sleep 500 |
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| 123 | |
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| 124 | echo "toggle trst" |
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| 125 | jtag_reset 1 1 0 1 |
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| 126 | |
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| 127 | echo "srst high" |
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| 128 | jtag_reset 0 0 |
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| 129 | sleep 10 |
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| 130 | } |
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| 131 | |
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| 132 | proc jtag_init {} { |
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| 133 | init_reset startup |
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| 134 | jtag arp_init |
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| 135 | } |
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