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1<!-- Copyright (C) 2007 Red Hat, Inc.                                -->
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9<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
10<HTML
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12><TITLE
13>Intel Xscale Generic Residential Gateway</TITLE
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25TITLE="Intel Xscale IXDP425 Network Processor Evaluation Board"
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28TITLE="Intel IXDPG425 Network Gateway Reference Platform"
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45><TR
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47COLSPAN="3"
48ALIGN="center"
49>RedBoot&#8482; User's Guide: Document Version 2.04, February 2007</TH
50></TR
51><TR
52><TD
53WIDTH="10%"
54ALIGN="left"
55VALIGN="bottom"
56><A
57HREF="ixdp425.html"
58ACCESSKEY="P"
59>Prev</A
60></TD
61><TD
62WIDTH="80%"
63ALIGN="center"
64VALIGN="bottom"
65>Chapter 5. Installation and Testing</TD
66><TD
67WIDTH="10%"
68ALIGN="right"
69VALIGN="bottom"
70><A
71HREF="ixdpg425.html"
72ACCESSKEY="N"
73>Next</A
74></TD
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77><HR
78ALIGN="LEFT"
79WIDTH="100%"></DIV
80><DIV
81CLASS="SECT1"
82><H1
83CLASS="SECT1"
84><A
85NAME="GRG"
86>Intel Xscale Generic Residential Gateway</A
87></H1
88><DIV
89CLASS="SECT2"
90><H2
91CLASS="SECT2"
92><A
93NAME="AEN1396"
94>Overview</A
95></H2
96><P
97>RedBoot supports
98the console UART, a PCI based i82559 ethernet card (i82559_eth0), and
99both NPE ethernet ports (npe_eth0 and npe_eth1) for communication and
100downloads. The default serial port settings are 115200,8,N,1. RedBoot
101also supports flash management for the 16MiB onboard flash. </P
102><P
103>The following RedBoot configurations are supported:
104
105      <DIV
106CLASS="INFORMALTABLE"
107><P
108></P
109><A
110NAME="AEN1406"
111></A
112><TABLE
113BORDER="1"
114FRAME="border"
115RULES="all"
116CLASS="CALSTABLE"
117><COL><COL><COL><COL><THEAD
118><TR
119><TH
120>Configuration</TH
121><TH
122>Mode</TH
123><TH
124>Description</TH
125><TH
126>File</TH
127></TR
128></THEAD
129><TBODY
130><TR
131><TD
132>ROM</TD
133><TD
134>[ROM]</TD
135><TD
136>RedBoot running from flash boot sector.</TD
137><TD
138>redboot_ROM.ecm</TD
139></TR
140><TR
141><TD
142>RAM</TD
143><TD
144>[RAM]</TD
145><TD
146>RedBoot running from RAM with RedBoot in the flash boot sector.</TD
147><TD
148>redboot_RAM.ecm</TD
149></TR
150></TBODY
151></TABLE
152><P
153></P
154></DIV
155></P
156></DIV
157><DIV
158CLASS="SECT2"
159><H2
160CLASS="SECT2"
161><A
162NAME="AEN1425"
163>Initial Installation Method</A
164></H2
165><P
166>The GRG flash is socketed, so initial installation may be done using
167an appropriate device programmer. JTAG based flash programming may also be
168used. In either case, the ROM mode RedBoot is programmed into the boot flash
169at address 0x00000000.</P
170><P
171>After booting the initial installation of RedBoot, this warning may
172be printed: <TABLE
173BORDER="5"
174BGCOLOR="#E0E0F0"
175WIDTH="70%"
176><TR
177><TD
178><PRE
179CLASS="SCREEN"
180>flash configuration checksum error or invalid key</PRE
181></TD
182></TR
183></TABLE
184>This is normal, and indicates that the flash should be configured
185for use by RedBoot. Even if this message is not seen, it is recommended that
186the <B
187CLASS="COMMAND"
188>fconfig</B
189> be run to initialize the flash configuration
190area. See <A
191HREF="persistent-state-flash.html"
192>the Section called <I
193>Persistent State Flash-based Configuration and Control</I
194> in Chapter 2</A
195> for more
196details.</P
197></DIV
198><DIV
199CLASS="SECT2"
200><H2
201CLASS="SECT2"
202><A
203NAME="AEN1432"
204>Rebuilding RedBoot</A
205></H2
206><P
207>These shell variables provide the platform-specific information
208needed for building RedBoot according to the procedure described in
209<A
210HREF="rebuilding-redboot.html"
211>Chapter 3</A
212>:
213<TABLE
214BORDER="5"
215BGCOLOR="#E0E0F0"
216WIDTH="70%"
217><TR
218><TD
219><PRE
220CLASS="PROGRAMLISTING"
221>export TARGET=grg
222export ARCH_DIR=arm
223export PLATFORM_DIR=xscale/grg</PRE
224></TD
225></TR
226></TABLE
227>
228Optionally, <TABLE
229BORDER="5"
230BGCOLOR="#E0E0F0"
231WIDTH="70%"
232><TR
233><TD
234><PRE
235CLASS="PROGRAMLISTING"
236>export TARGET=grg_npe</PRE
237></TD
238></TR
239></TABLE
240>
241could be used to include NPE ethernet support.</P
242><P
243>The names of configuration files are listed above with the
244description of the associated modes.</P
245></DIV
246><DIV
247CLASS="SECT2"
248><H2
249CLASS="SECT2"
250><A
251NAME="AEN1439"
252>Interrupts</A
253></H2
254><P
255>RedBoot uses an interrupt vector table which is located at address 0x8004.
256Entries in this table are pointers to functions with this protoype::      <TABLE
257BORDER="5"
258BGCOLOR="#E0E0F0"
259WIDTH="70%"
260><TR
261><TD
262><PRE
263CLASS="PROGRAMLISTING"
264>int irq_handler( unsigned vector, unsigned data )</PRE
265></TD
266></TR
267></TABLE
268>On the GRG
269board, the vector argument is one of many interrupts defined in <SAMP
270CLASS="COMPUTEROUTPUT"
271>hal/arm/xscale/bulverde/current/include/hal_var_ints.h:</SAMP
272>:   <TABLE
273BORDER="5"
274BGCOLOR="#E0E0F0"
275WIDTH="70%"
276><TR
277><TD
278><PRE
279CLASS="PROGRAMLISTING"
280>#define CYGNUM_HAL_INTERRUPT_NPEA         0
281#define CYGNUM_HAL_INTERRUPT_NPEB         1
282#define CYGNUM_HAL_INTERRUPT_NPEC         2
283#define CYGNUM_HAL_INTERRUPT_QM1          3
284#define CYGNUM_HAL_INTERRUPT_QM2          4
285#define CYGNUM_HAL_INTERRUPT_TIMER0       5
286#define CYGNUM_HAL_INTERRUPT_GPIO0        6
287#define CYGNUM_HAL_INTERRUPT_GPIO1        7
288#define CYGNUM_HAL_INTERRUPT_PCI_INT      8
289#define CYGNUM_HAL_INTERRUPT_PCI_DMA1     9
290#define CYGNUM_HAL_INTERRUPT_PCI_DMA2     10
291#define CYGNUM_HAL_INTERRUPT_TIMER1       11
292#define CYGNUM_HAL_INTERRUPT_USB          12
293#define CYGNUM_HAL_INTERRUPT_UART2        13
294#define CYGNUM_HAL_INTERRUPT_TIMESTAMP    14
295#define CYGNUM_HAL_INTERRUPT_UART1        15
296#define CYGNUM_HAL_INTERRUPT_WDOG         16
297#define CYGNUM_HAL_INTERRUPT_AHB_PMU      17
298#define CYGNUM_HAL_INTERRUPT_XSCALE_PMU   18
299#define CYGNUM_HAL_INTERRUPT_GPIO2        19
300#define CYGNUM_HAL_INTERRUPT_GPIO3        20
301#define CYGNUM_HAL_INTERRUPT_GPIO4        21
302#define CYGNUM_HAL_INTERRUPT_GPIO5        22
303#define CYGNUM_HAL_INTERRUPT_GPIO6        23
304#define CYGNUM_HAL_INTERRUPT_GPIO7        24
305#define CYGNUM_HAL_INTERRUPT_GPIO8        25
306#define CYGNUM_HAL_INTERRUPT_GPIO9        26
307#define CYGNUM_HAL_INTERRUPT_GPIO10       27
308#define CYGNUM_HAL_INTERRUPT_GPIO11       28           
309#define CYGNUM_HAL_INTERRUPT_GPIO12       29
310#define CYGNUM_HAL_INTERRUPT_SW_INT1      30
311#define CYGNUM_HAL_INTERRUPT_SW_INT2      31</PRE
312></TD
313></TR
314></TABLE
315>
316The data passed to the ISR is pulled from a data table <SAMP
317CLASS="COMPUTEROUTPUT"
318>(hal_interrupt_data)</SAMP
319> which immediately follows the interrupt vector table. With
32032 interrupts, the data table starts at address 0x8084.   </P
321><P
322>An application may create a normal C function with the above prototype
323to be an ISR. Just poke its address into the table at the correct index and
324enable the interrupt at its source. The return value of the ISR is ignored
325by RedBoot.</P
326></DIV
327><DIV
328CLASS="SECT2"
329><H2
330CLASS="SECT2"
331><A
332NAME="AEN1447"
333>Memory Maps</A
334></H2
335><P
336>The RAM based page table is located at RAM start + 0x4000.
337<DIV
338CLASS="NOTE"
339><BLOCKQUOTE
340CLASS="NOTE"
341><P
342><B
343>NOTE: </B
344>The virtual memory maps in this section use a C, B, and X column to indicate
345the caching policy for the region..</P
346></BLOCKQUOTE
347></DIV
348></P
349><P
350><TABLE
351BORDER="5"
352BGCOLOR="#E0E0F0"
353WIDTH="70%"
354><TR
355><TD
356><PRE
357CLASS="PROGRAMLISTING"
358>X C B  Description
359- - -  ---------------------------------------------
3600 0 0  Uncached/Unbuffered
3610 0 1  Uncached/Buffered
3620 1 0  Cached/Buffered    Write Through, Read Allocate
3630 1 1  Cached/Buffered    Write Back, Read Allocate
3641 0 0  Invalid -- not used
3651 0 1  Uncached/Buffered  No write buffer coalescing
3661 1 0  Mini DCache - Policy set by Aux Ctl Register
3671 1 1  Cached/Buffered    Write Back, Read/Write Allocate
368
369Virtual Address   Physical Address  XCB  Size (MiB) Description
370---------------   ----------------  ---  ---------  -----------
371   0x00000000       0x00000000      010      32     SDRAM (cached)
372   0x10000000       0x00000000      010      32     SDRAM (alias)
373   0x20000000       0x00000000      000      32     SDRAM (uncached)
374   0x48000000       0x48000000      000      64     PCI Data
375   0x50000000       0x50000000      010      16     Flash (CS0)
376   0x51000000       0x51000000      000     112     CS1 - CS7
377   0x60000000       0x60000000      000      64     Queue Manager
378   0xC0000000       0xC0000000      000       1     PCI Controller
379   0xC4000000       0xC4000000      000       1     Exp. Bus Config
380   0xC8000000       0xC8000000      000       1     Misc CPU IO
381   0xCC000000       0xCC000000      000       1     SDRAM Config&#13;</PRE
382></TD
383></TR
384></TABLE
385></P
386></DIV
387><DIV
388CLASS="SECT2"
389><H2
390CLASS="SECT2"
391><A
392NAME="AEN1455"
393>Platform Resource Usage</A
394></H2
395><P
396>The IXP425 programmable OStimer0 is used for timeout support
397for networking and XModem file transfers.</P
398></DIV
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