source: SVN/cambria/redboot/docs/redboot/html/hamoa.html @ 1

Last change on this file since 1 was 1, checked in by Tim Harvey, 2 years ago

restored latest version of files from server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 13.3 KB
Line 
1<!-- Copyright (C) 2007 Red Hat, Inc.                                -->
2<!-- This material may be distributed only subject to the terms      -->
3<!-- and conditions set forth in the Open Publication License, v1.0  -->
4<!-- or later (the latest version is presently available at          -->
5<!-- http://www.opencontent.org/openpub/).                           -->
6<!-- Distribution of the work or derivative of the work in any       -->
7<!-- standard (paper) book form is prohibited unless prior           -->
8<!-- permission is obtained from the copyright holder.               -->
9<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
10<HTML
11><HEAD
12><TITLE
13>Intel(r) Next Generation of Network Processors (Code Name Hamoa)
14Reference Platform</TITLE
15><meta name="MSSmartTagsPreventParsing" content="TRUE">
16<META
17NAME="GENERATOR"
18CONTENT="Modular DocBook HTML Stylesheet Version 1.79"><LINK
19REL="HOME"
20TITLE="RedBoot&#8482; User's Guide"
21HREF="redboot.html"><LINK
22REL="UP"
23TITLE="Installation and Testing"
24HREF="installation-and-testing.html"><LINK
25REL="PREVIOUS"
26TITLE="Installation and Testing"
27HREF="installation-and-testing.html"><LINK
28REL="NEXT"
29TITLE="Intel Xscale IXDP425 Network Processor Evaluation Board"
30HREF="ixdp425.html"></HEAD
31><BODY
32CLASS="SECT1"
33BGCOLOR="#FFFFFF"
34TEXT="#000000"
35LINK="#0000FF"
36VLINK="#840084"
37ALINK="#0000FF"
38><DIV
39CLASS="NAVHEADER"
40><TABLE
41SUMMARY="Header navigation table"
42WIDTH="100%"
43BORDER="0"
44CELLPADDING="0"
45CELLSPACING="0"
46><TR
47><TH
48COLSPAN="3"
49ALIGN="center"
50>RedBoot&#8482; User's Guide: Document Version 2.04, February 2007</TH
51></TR
52><TR
53><TD
54WIDTH="10%"
55ALIGN="left"
56VALIGN="bottom"
57><A
58HREF="installation-and-testing.html"
59ACCESSKEY="P"
60>Prev</A
61></TD
62><TD
63WIDTH="80%"
64ALIGN="center"
65VALIGN="bottom"
66>Chapter 5. Installation and Testing</TD
67><TD
68WIDTH="10%"
69ALIGN="right"
70VALIGN="bottom"
71><A
72HREF="ixdp425.html"
73ACCESSKEY="N"
74>Next</A
75></TD
76></TR
77></TABLE
78><HR
79ALIGN="LEFT"
80WIDTH="100%"></DIV
81><DIV
82CLASS="SECT1"
83><H1
84CLASS="SECT1"
85><A
86NAME="HAMOA"
87>Intel(r) Next Generation of Network Processors (Code Name Hamoa)
88Reference Platform</A
89></H1
90><DIV
91CLASS="SECT2"
92><H2
93CLASS="SECT2"
94><A
95NAME="AEN1249"
96>Overview</A
97></H2
98><P
99>RedBoot supports
100the builtin high-speed UART, a single PCI based E100 (i82559_eth0), a single
101PCI based E1000 ethernet card (e1000_eth0), and both NPE ethernet ports (npe_wan
102and npe_lan) for communication and downloads. The default serial port settings
103are 115200,8,N,1. RedBoot also supports flash management for the 16MiB boot
104flash on the board.</P
105><P
106>The following RedBoot configurations are supported:
107
108      <DIV
109CLASS="INFORMALTABLE"
110><P
111></P
112><A
113NAME="AEN1259"
114></A
115><TABLE
116BORDER="1"
117FRAME="border"
118RULES="all"
119CLASS="CALSTABLE"
120><COL><COL><COL><COL><THEAD
121><TR
122><TH
123>Configuration</TH
124><TH
125>Mode</TH
126><TH
127>Description</TH
128><TH
129>File</TH
130></TR
131></THEAD
132><TBODY
133><TR
134><TD
135>ROM</TD
136><TD
137>[ROM]</TD
138><TD
139>RedBoot running from flash boot sector.</TD
140><TD
141>redboot_ROM.ecm</TD
142></TR
143><TR
144><TD
145>RAM</TD
146><TD
147>[RAM]</TD
148><TD
149>RedBoot running from RAM with RedBoot in the flash boot sector.</TD
150><TD
151>redboot_RAM.ecm</TD
152></TR
153><TR
154><TD
155>ROMRAM</TD
156><TD
157>[ROMRAM]</TD
158><TD
159>RedBoot booting from flash, running from RAM.
160              </TD
161><TD
162>redboot_ROMRAM.ecm</TD
163></TR
164></TBODY
165></TABLE
166><P
167></P
168></DIV
169></P
170></DIV
171><DIV
172CLASS="SECT2"
173><H2
174CLASS="SECT2"
175><A
176NAME="AEN1283"
177>Initial Installation Method</A
178></H2
179><P
180>The onboard flash is not socketed, so initial installation must be done
181using an appropriate JTAG based solution. The ROM or ROMRAM mode RedBoot images
182are programmed into the boot flash at offset 0x00000000.</P
183><P
184>After booting the initial installation of RedBoot, this warning may
185be printed: <TABLE
186BORDER="5"
187BGCOLOR="#E0E0F0"
188WIDTH="70%"
189><TR
190><TD
191><PRE
192CLASS="SCREEN"
193>flash configuration checksum error or invalid key</PRE
194></TD
195></TR
196></TABLE
197>This is normal, and indicates that the flash should be configured
198for use by RedBoot. Even if this message is not seen, it is recommended that
199<B
200CLASS="COMMAND"
201>fconfig</B
202> be run to initialize the flash configuration
203area. See <A
204HREF="persistent-state-flash.html"
205>the Section called <I
206>Persistent State Flash-based Configuration and Control</I
207> in Chapter 2</A
208> for more details.</P
209></DIV
210><DIV
211CLASS="SECT2"
212><H2
213CLASS="SECT2"
214><A
215NAME="AEN1290"
216>LED Codes</A
217></H2
218><P
219>RedBoot uses 8 discrete LEDs to indicate an 8 bit status code
220during board initialization. The LEDs are arranged as two rows of
221four LEDs. The top row of LEDs are the most significant 4 bits
222of the status code and the bottom row are the least significant 4
223bits. Possible codes are:</P
224><P
225CLASS="LITERALLAYOUT"
226>LED&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Actions<br>
227-------------------------------------------------------------<br>
228&nbsp;&nbsp;    Power-On/Reset<br>
229&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Set&nbsp;the&nbsp;CPSR<br>
230&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Enable&nbsp;coprocessor&nbsp;access<br>
231&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Drain&nbsp;write&nbsp;and&nbsp;fill&nbsp;buffer<br>
232&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Setup&nbsp;expansion&nbsp;bus&nbsp;chip&nbsp;selects<br>
233F1<br>
234&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Enable&nbsp;Icache<br>
235F2<br>
236&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Initialize&nbsp;SDRAM&nbsp;controller<br>
237F3<br>
238&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Initialize&nbsp;hardware&nbsp;registers.<br>
239F4<br>
240&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Switch&nbsp;flash&nbsp;(CS0)&nbsp;from&nbsp;0x00000000&nbsp;to&nbsp;0x50000000<br>
241F5<br>
242&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[ROMRAM&nbsp;only]&nbsp;Copy&nbsp;RedBoot&nbsp;to&nbsp;SDRAM&nbsp;and&nbsp;execute&nbsp;from&nbsp;there<br>
243F6<br>
244&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Build&nbsp;MMU&nbsp;table&nbsp;in&nbsp;SDRAM<br>
245F7<br>
246&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Setup&nbsp;TTB&nbsp;to&nbsp;point&nbsp;to&nbsp;page&nbsp;table<br>
247F8<br>
248&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Turn&nbsp;on&nbsp;MMU<br>
249F9<br>
250&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Enable&nbsp;DCache<br>
251FA<br>
252&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Enable&nbsp;branch&nbsp;target&nbsp;buffer<br>
253FB<br>
254&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Drain&nbsp;write&nbsp;and&nbsp;fill&nbsp;buffer<br>
255&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Flush&nbsp;caches<br>
256FC<br>
257&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Set&nbsp;up&nbsp;low&nbsp;level&nbsp;vectors.<br>
25803<br>
259&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;initialize&nbsp;PCI&nbsp;bus.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<br>
26001<br>
261&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Start&nbsp;RedBoot&nbsp;command&nbsp;shell.<br>&#13;</P
262></DIV
263><DIV
264CLASS="SECT2"
265><H2
266CLASS="SECT2"
267><A
268NAME="AEN1294"
269>Rebuilding RedBoot</A
270></H2
271><P
272>These shell variables provide the platform-specific information
273needed for building RedBoot according to the procedure described in
274<A
275HREF="rebuilding-redboot.html"
276>Chapter 3</A
277>:
278<TABLE
279BORDER="5"
280BGCOLOR="#E0E0F0"
281WIDTH="70%"
282><TR
283><TD
284><PRE
285CLASS="PROGRAMLISTING"
286>export TARGET=kixrp435
287export ARCH_DIR=arm
288export PLATFORM_DIR=xscale/kixrp435</PRE
289></TD
290></TR
291></TABLE
292>
293Optionally, <TABLE
294BORDER="5"
295BGCOLOR="#E0E0F0"
296WIDTH="70%"
297><TR
298><TD
299><PRE
300CLASS="PROGRAMLISTING"
301>export TARGET=kixrp435_npe</PRE
302></TD
303></TR
304></TABLE
305>
306could be used to include NPE ethernet support.</P
307><P
308>The names of configuration files are listed above with the
309description of the associated modes.</P
310></DIV
311><DIV
312CLASS="SECT2"
313><H2
314CLASS="SECT2"
315><A
316NAME="AEN1301"
317>Interrupts</A
318></H2
319><P
320>RedBoot uses an interrupt vector table which is located at address 0x8004.
321Entries in this table are pointers to functions with this protoype::      <TABLE
322BORDER="5"
323BGCOLOR="#E0E0F0"
324WIDTH="70%"
325><TR
326><TD
327><PRE
328CLASS="PROGRAMLISTING"
329>int irq_handler( unsigned vector, unsigned data )</PRE
330></TD
331></TR
332></TABLE
333>On the
334Intel(r) Next Generation of Network Processors (Code Name Hamoa) Reference Platform,
335the vector argument is one of many interrupts defined in <SAMP
336CLASS="COMPUTEROUTPUT"
337>hal/arm/xscale/ixp425/current/include/hal_var_ints.h:</SAMP
338>:   <TABLE
339BORDER="5"
340BGCOLOR="#E0E0F0"
341WIDTH="70%"
342><TR
343><TD
344><PRE
345CLASS="PROGRAMLISTING"
346>#define CYGNUM_HAL_INTERRUPT_NPEA         0
347#define CYGNUM_HAL_INTERRUPT_NPEB         1
348#define CYGNUM_HAL_INTERRUPT_NPEC         2
349#define CYGNUM_HAL_INTERRUPT_QM1          3
350#define CYGNUM_HAL_INTERRUPT_QM2          4
351#define CYGNUM_HAL_INTERRUPT_TIMER0       5
352#define CYGNUM_HAL_INTERRUPT_GPIO0        6
353#define CYGNUM_HAL_INTERRUPT_GPIO1        7
354#define CYGNUM_HAL_INTERRUPT_PCI_INT      8
355#define CYGNUM_HAL_INTERRUPT_PCI_DMA1     9
356#define CYGNUM_HAL_INTERRUPT_PCI_DMA2     10
357#define CYGNUM_HAL_INTERRUPT_TIMER1       11
358#define CYGNUM_HAL_INTERRUPT_USB          12
359#define CYGNUM_HAL_INTERRUPT_UART2        13
360#define CYGNUM_HAL_INTERRUPT_TIMESTAMP    14
361#define CYGNUM_HAL_INTERRUPT_UART1        15
362#define CYGNUM_HAL_INTERRUPT_WDOG         16
363#define CYGNUM_HAL_INTERRUPT_AHB_PMU      17
364#define CYGNUM_HAL_INTERRUPT_XSCALE_PMU   18
365#define CYGNUM_HAL_INTERRUPT_GPIO2        19
366#define CYGNUM_HAL_INTERRUPT_GPIO3        20
367#define CYGNUM_HAL_INTERRUPT_GPIO4        21
368#define CYGNUM_HAL_INTERRUPT_GPIO5        22
369#define CYGNUM_HAL_INTERRUPT_GPIO6        23
370#define CYGNUM_HAL_INTERRUPT_GPIO7        24
371#define CYGNUM_HAL_INTERRUPT_GPIO8        25
372#define CYGNUM_HAL_INTERRUPT_GPIO9        26
373#define CYGNUM_HAL_INTERRUPT_GPIO10       27
374#define CYGNUM_HAL_INTERRUPT_GPIO11       28           
375#define CYGNUM_HAL_INTERRUPT_GPIO12       29
376#define CYGNUM_HAL_INTERRUPT_SW_INT1      30
377#define CYGNUM_HAL_INTERRUPT_SW_INT2      31
378#define CYGNUM_HAL_INTERRUPT_USB_HOST     32
379#define CYGNUM_HAL_INTERRUPT_I2C          33
380#define CYGNUM_HAL_INTERRUPT_SPI          34
381#define CYGNUM_HAL_INTERRUPT_TIMESYNC     35
382#define CYGNUM_HAL_INTERRUPT_EAU_DONE     36
383#define CYGNUM_HAL_INTERRUPT_SHA_DONE     37
384#define CYGNUM_HAL_INTERRUPT_SWCP_PERR    58
385#define CYGNUM_HAL_INTERRUPT_QMGR_PERR    60
386#define CYGNUM_HAL_INTERRUPT_MCU_ERR      61
387#define CYGNUM_HAL_INTERRUPT_EXP_PERR     62</PRE
388></TD
389></TR
390></TABLE
391>
392The data passed to the ISR is pulled from a data table <SAMP
393CLASS="COMPUTEROUTPUT"
394>(hal_interrupt_data)</SAMP
395> which immediately follows the interrupt vector table. With
39664 interrupts, the data table starts at address 0x8104.   </P
397><P
398>An application may create a normal C function with the above prototype
399to be an ISR. Just poke its address into the table at the correct index and
400enable the interrupt at its source. The return value of the ISR is ignored
401by RedBoot.</P
402></DIV
403><DIV
404CLASS="SECT2"
405><H2
406CLASS="SECT2"
407><A
408NAME="AEN1309"
409>Memory Maps</A
410></H2
411><P
412>The RAM based page table is located at RAM start + 0x4000.
413<DIV
414CLASS="NOTE"
415><BLOCKQUOTE
416CLASS="NOTE"
417><P
418><B
419>NOTE: </B
420>The virtual memory maps in this section use a C, B, and X column to indicate
421the caching policy for the region..</P
422></BLOCKQUOTE
423></DIV
424></P
425><P
426><TABLE
427BORDER="5"
428BGCOLOR="#E0E0F0"
429WIDTH="70%"
430><TR
431><TD
432><PRE
433CLASS="PROGRAMLISTING"
434>X C B  Description
435- - -  ---------------------------------------------
4360 0 0  Uncached/Unbuffered
4370 0 1  Uncached/Buffered
4380 1 0  Cached/Buffered    Write Through, Read Allocate
4390 1 1  Cached/Buffered    Write Back, Read Allocate
4401 0 0  Invalid -- not used
4411 0 1  Uncached/Buffered  No write buffer coalescing
4421 1 0  Mini DCache - Policy set by Aux Ctl Register
4431 1 1  Cached/Buffered    Write Back, Read/Write Allocate
444
445Virtual Address   Physical Address  XCB  Size (MiB) Description
446---------------   ----------------  ---  ---------  -----------
447   0x00000000       0x00000000      010     128     SDRAM (cached)
448   0x20000000       0x00000000      000     128     SDRAM (uncached)
449   0x30000000       0x00000000      010     128     SDRAM (cached data coherent)
450   0x48000000       0x48000000      000      64     PCI Data
451   0x50000000       0x50000000      010      16     Flash (CS0)
452   0x51000000       0x51000000      000     112     CS1 - CS4
453   0x60000000       0x60000000      000      64     Queue Manager
454   0xA0000000       0x50000000      010      16     Flash (CS0, data coherent)
455   0xC0000000       0xC0000000      000       1     PCI Controller
456   0xC4000000       0xC4000000      000       1     Exp. Bus Config
457   0xC8000000       0xC8000000      000       1     Misc IXP4xx IO
458   0xCC000000       0xCC000000      000       1     SDRAM Config&#13;</PRE
459></TD
460></TR
461></TABLE
462></P
463></DIV
464><DIV
465CLASS="SECT2"
466><H2
467CLASS="SECT2"
468><A
469NAME="AEN1317"
470>Platform Resource Usage</A
471></H2
472><P
473>The IXP4xx programmable OStimer0 is used for timeout support
474for networking and XModem file transfers.</P
475></DIV
476></DIV
477><DIV
478CLASS="NAVFOOTER"
479><HR
480ALIGN="LEFT"
481WIDTH="100%"><TABLE
482SUMMARY="Footer navigation table"
483WIDTH="100%"
484BORDER="0"
485CELLPADDING="0"
486CELLSPACING="0"
487><TR
488><TD
489WIDTH="33%"
490ALIGN="left"
491VALIGN="top"
492><A
493HREF="installation-and-testing.html"
494ACCESSKEY="P"
495>Prev</A
496></TD
497><TD
498WIDTH="34%"
499ALIGN="center"
500VALIGN="top"
501><A
502HREF="redboot.html"
503ACCESSKEY="H"
504>Home</A
505></TD
506><TD
507WIDTH="33%"
508ALIGN="right"
509VALIGN="top"
510><A
511HREF="ixdp425.html"
512ACCESSKEY="N"
513>Next</A
514></TD
515></TR
516><TR
517><TD
518WIDTH="33%"
519ALIGN="left"
520VALIGN="top"
521>Installation and Testing</TD
522><TD
523WIDTH="34%"
524ALIGN="center"
525VALIGN="top"
526><A
527HREF="installation-and-testing.html"
528ACCESSKEY="U"
529>Up</A
530></TD
531><TD
532WIDTH="33%"
533ALIGN="right"
534VALIGN="top"
535>Intel Xscale IXDP425 Network Processor Evaluation Board</TD
536></TR
537></TABLE
538></DIV
539></BODY
540></HTML
541>
Note: See TracBrowser for help on using the repository browser.