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1<!-- Copyright (C) 2007 Red Hat, Inc.                                -->
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9<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
10<HTML
11><HEAD
12><TITLE
13>Intel IXDPG425 Network Gateway Reference Platform</TITLE
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46>RedBoot&#8482; User's Guide: Document Version 2.04, February 2007</TH
47></TR
48><TR
49><TD
50WIDTH="10%"
51ALIGN="left"
52VALIGN="bottom"
53><A
54HREF="grg.html"
55ACCESSKEY="P"
56>Prev</A
57></TD
58><TD
59WIDTH="80%"
60ALIGN="center"
61VALIGN="bottom"
62>Chapter 5. Installation and Testing</TD
63><TD
64WIDTH="10%"
65ALIGN="right"
66VALIGN="bottom"
67>&nbsp;</TD
68></TR
69></TABLE
70><HR
71ALIGN="LEFT"
72WIDTH="100%"></DIV
73><DIV
74CLASS="SECT1"
75><H1
76CLASS="SECT1"
77><A
78NAME="IXDPG425"
79>Intel IXDPG425 Network Gateway Reference Platform</A
80></H1
81><DIV
82CLASS="SECT2"
83><H2
84CLASS="SECT2"
85><A
86NAME="AEN1460"
87>Overview</A
88></H2
89><P
90>RedBoot supports
91the high-speed UART and NPE ethernet ports (npe_eth0 and npe_eth1) for
92communication and downloads. The default serial port settings are 115200,8,N,1.
93RedBoot also supports flash management for the 16MiB onboard flash. </P
94><P
95>The following RedBoot configurations are supported:
96
97      <DIV
98CLASS="INFORMALTABLE"
99><P
100></P
101><A
102NAME="AEN1470"
103></A
104><TABLE
105BORDER="1"
106FRAME="border"
107RULES="all"
108CLASS="CALSTABLE"
109><COL><COL><COL><COL><THEAD
110><TR
111><TH
112>Configuration</TH
113><TH
114>Mode</TH
115><TH
116>Description</TH
117><TH
118>File</TH
119></TR
120></THEAD
121><TBODY
122><TR
123><TD
124>ROM</TD
125><TD
126>[ROM]</TD
127><TD
128>RedBoot running from flash boot sector.</TD
129><TD
130>redboot_ROM.ecm</TD
131></TR
132><TR
133><TD
134>RAM</TD
135><TD
136>[RAM]</TD
137><TD
138>RedBoot running from RAM with RedBoot in the flash boot sector.</TD
139><TD
140>redboot_RAM.ecm</TD
141></TR
142></TBODY
143></TABLE
144><P
145></P
146></DIV
147></P
148></DIV
149><DIV
150CLASS="SECT2"
151><H2
152CLASS="SECT2"
153><A
154NAME="AEN1489"
155>Initial Installation Method</A
156></H2
157><P
158>The IXDPG425 flash is socketed, so initial installation may be done using
159an appropriate device programmer. JTAG based flash programming may also be
160used. In either case, the ROM mode RedBoot is programmed into the boot flash
161at address 0x00000000.</P
162><P
163>After booting the initial installation of RedBoot, this warning may
164be printed: <TABLE
165BORDER="5"
166BGCOLOR="#E0E0F0"
167WIDTH="70%"
168><TR
169><TD
170><PRE
171CLASS="SCREEN"
172>flash configuration checksum error or invalid key</PRE
173></TD
174></TR
175></TABLE
176>This is normal, and indicates that the flash should be configured
177for use by RedBoot. Even if this message is not seen, it is recommended that
178the <B
179CLASS="COMMAND"
180>fconfig</B
181> be run to initialize the flash configuration
182area. See <A
183HREF="persistent-state-flash.html"
184>the Section called <I
185>Persistent State Flash-based Configuration and Control</I
186> in Chapter 2</A
187> for more
188details.</P
189></DIV
190><DIV
191CLASS="SECT2"
192><H2
193CLASS="SECT2"
194><A
195NAME="AEN1496"
196>Rebuilding RedBoot</A
197></H2
198><P
199>These shell variables provide the platform-specific information
200needed for building RedBoot according to the procedure described in
201<A
202HREF="rebuilding-redboot.html"
203>Chapter 3</A
204>:
205<TABLE
206BORDER="5"
207BGCOLOR="#E0E0F0"
208WIDTH="70%"
209><TR
210><TD
211><PRE
212CLASS="PROGRAMLISTING"
213>export TARGET=ixdpg425
214export ARCH_DIR=arm
215export PLATFORM_DIR=xscale/ixdpg425</PRE
216></TD
217></TR
218></TABLE
219>
220Optionally, <TABLE
221BORDER="5"
222BGCOLOR="#E0E0F0"
223WIDTH="70%"
224><TR
225><TD
226><PRE
227CLASS="PROGRAMLISTING"
228>export TARGET=ixdpg425_npe</PRE
229></TD
230></TR
231></TABLE
232>
233could be used to include NPE ethernet support.</P
234><P
235>The names of configuration files are listed above with the
236description of the associated modes.</P
237></DIV
238><DIV
239CLASS="SECT2"
240><H2
241CLASS="SECT2"
242><A
243NAME="AEN1503"
244>Interrupts</A
245></H2
246><P
247>RedBoot uses an interrupt vector table which is located at address 0x8004.
248Entries in this table are pointers to functions with this protoype::      <TABLE
249BORDER="5"
250BGCOLOR="#E0E0F0"
251WIDTH="70%"
252><TR
253><TD
254><PRE
255CLASS="PROGRAMLISTING"
256>int irq_handler( unsigned vector, unsigned data )</PRE
257></TD
258></TR
259></TABLE
260>On the IXDPG425
261board, the vector argument is one of many interrupts defined in <SAMP
262CLASS="COMPUTEROUTPUT"
263>hal/arm/xscale/ixp425/current/include/hal_var_ints.h:</SAMP
264>:   <TABLE
265BORDER="5"
266BGCOLOR="#E0E0F0"
267WIDTH="70%"
268><TR
269><TD
270><PRE
271CLASS="PROGRAMLISTING"
272>#define CYGNUM_HAL_INTERRUPT_NPEA         0
273#define CYGNUM_HAL_INTERRUPT_NPEB         1
274#define CYGNUM_HAL_INTERRUPT_NPEC         2
275#define CYGNUM_HAL_INTERRUPT_QM1          3
276#define CYGNUM_HAL_INTERRUPT_QM2          4
277#define CYGNUM_HAL_INTERRUPT_TIMER0       5
278#define CYGNUM_HAL_INTERRUPT_GPIO0        6
279#define CYGNUM_HAL_INTERRUPT_GPIO1        7
280#define CYGNUM_HAL_INTERRUPT_PCI_INT      8
281#define CYGNUM_HAL_INTERRUPT_PCI_DMA1     9
282#define CYGNUM_HAL_INTERRUPT_PCI_DMA2     10
283#define CYGNUM_HAL_INTERRUPT_TIMER1       11
284#define CYGNUM_HAL_INTERRUPT_USB          12
285#define CYGNUM_HAL_INTERRUPT_UART2        13
286#define CYGNUM_HAL_INTERRUPT_TIMESTAMP    14
287#define CYGNUM_HAL_INTERRUPT_UART1        15
288#define CYGNUM_HAL_INTERRUPT_WDOG         16
289#define CYGNUM_HAL_INTERRUPT_AHB_PMU      17
290#define CYGNUM_HAL_INTERRUPT_XSCALE_PMU   18
291#define CYGNUM_HAL_INTERRUPT_GPIO2        19
292#define CYGNUM_HAL_INTERRUPT_GPIO3        20
293#define CYGNUM_HAL_INTERRUPT_GPIO4        21
294#define CYGNUM_HAL_INTERRUPT_GPIO5        22
295#define CYGNUM_HAL_INTERRUPT_GPIO6        23
296#define CYGNUM_HAL_INTERRUPT_GPIO7        24
297#define CYGNUM_HAL_INTERRUPT_GPIO8        25
298#define CYGNUM_HAL_INTERRUPT_GPIO9        26
299#define CYGNUM_HAL_INTERRUPT_GPIO10       27
300#define CYGNUM_HAL_INTERRUPT_GPIO11       28           
301#define CYGNUM_HAL_INTERRUPT_GPIO12       29
302#define CYGNUM_HAL_INTERRUPT_SW_INT1      30
303#define CYGNUM_HAL_INTERRUPT_SW_INT2      31</PRE
304></TD
305></TR
306></TABLE
307>
308The data passed to the ISR is pulled from a data table <SAMP
309CLASS="COMPUTEROUTPUT"
310>(hal_interrupt_data)</SAMP
311> which immediately follows the interrupt vector table. With
31232 interrupts, the data table starts at address 0x8084.   </P
313><P
314>An application may create a normal C function with the above prototype
315to be an ISR. Just poke its address into the table at the correct index and
316enable the interrupt at its source. The return value of the ISR is ignored
317by RedBoot.</P
318></DIV
319><DIV
320CLASS="SECT2"
321><H2
322CLASS="SECT2"
323><A
324NAME="AEN1511"
325>Memory Maps</A
326></H2
327><P
328>The RAM based page table is located at RAM start + 0x4000.
329<DIV
330CLASS="NOTE"
331><BLOCKQUOTE
332CLASS="NOTE"
333><P
334><B
335>NOTE: </B
336>The virtual memory maps in this section use a C, B, and X column to indicate
337the caching policy for the region..</P
338></BLOCKQUOTE
339></DIV
340></P
341><P
342><TABLE
343BORDER="5"
344BGCOLOR="#E0E0F0"
345WIDTH="70%"
346><TR
347><TD
348><PRE
349CLASS="PROGRAMLISTING"
350>X C B  Description
351- - -  ---------------------------------------------
3520 0 0  Uncached/Unbuffered
3530 0 1  Uncached/Buffered
3540 1 0  Cached/Buffered    Write Through, Read Allocate
3550 1 1  Cached/Buffered    Write Back, Read Allocate
3561 0 0  Invalid -- not used
3571 0 1  Uncached/Buffered  No write buffer coalescing
3581 1 0  Mini DCache - Policy set by Aux Ctl Register
3591 1 1  Cached/Buffered    Write Back, Read/Write Allocate
360
361Virtual Address   Physical Address  XCB  Size (MiB) Description
362---------------   ----------------  ---  ---------  -----------
363   0x00000000       0x00000000      010      32     SDRAM (cached)
364   0x10000000       0x00000000      010      32     SDRAM (alias)
365   0x20000000       0x00000000      000      32     SDRAM (uncached)
366   0x30000000       0x00000000      010      32     SDRAM (data coherent)
367   0x48000000       0x48000000      000      64     PCI Data
368   0x50000000       0x50000000      010      16     Flash (CS0)
369   0x51000000       0x51000000      000     112     CS1 - CS7
370   0x60000000       0x60000000      000      64     Queue Manager
371   0xC0000000       0xC0000000      000       1     PCI Controller
372   0xC4000000       0xC4000000      000       1     Exp. Bus Config
373   0xC8000000       0xC8000000      000       1     Misc CPU IO
374   0xCC000000       0xCC000000      000       1     SDRAM Config&#13;</PRE
375></TD
376></TR
377></TABLE
378></P
379></DIV
380><DIV
381CLASS="SECT2"
382><H2
383CLASS="SECT2"
384><A
385NAME="AEN1519"
386>Platform Resource Usage</A
387></H2
388><P
389>The IXP425 programmable OStimer0 is used for timeout support
390for networking and XModem file transfers.</P
391></DIV
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