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1/**
2 * @file IxAtmTypes.h
3 *
4 * @date 24-MAR-2002
5 *
6 * @brief This file contains Atm types common to a number of Atm components.
7 *
8 * @par
9 * IXP400 SW Release version 2.3
10 *
11 * -- Copyright Notice --
12 *
13 * @par
14 * Copyright (c) 2001-2005, Intel Corporation.
15 * All rights reserved.
16 *
17 * @par
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions
20 * are met:
21 * 1. Redistributions of source code must retain the above copyright
22 *    notice, this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright
24 *    notice, this list of conditions and the following disclaimer in the
25 *    documentation and/or other materials provided with the distribution.
26 * 3. Neither the name of the Intel Corporation nor the names of its contributors
27 *    may be used to endorse or promote products derived from this software
28 *    without specific prior written permission.
29 *
30 *
31 * @par
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
35 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
42 * SUCH DAMAGE.
43 *
44 *
45 * @par
46 * -- End of Copyright Notice --
47 */
48
49/* ------------------------------------------------------
50   Doxygen group definitions
51   ------------------------------------------------------ */
52/**
53 * @defgroup IxAtmTypes Intel (R) IXP400 Software ATM Types (IxAtmTypes)
54 *
55 * @brief The common set of types used in many Atm components
56 *
57 * @{ */
58
59#ifndef IXATMTYPES_H
60#define IXATMTYPES_H
61
62#include "IxNpeA.h"
63
64/**
65 * @enum IxAtmLogicalPort
66 *
67 * @brief Logical Port Definitions  :
68 *
69 * Only 1 port is available in SPHY configuration
70 * 4 ports are enabled in ATMMPORT configuration
71 * 12 ports are enabled in MPHY configuration
72 *
73 */
74typedef enum
75{
76    IX_UTOPIA_PORT_0 = 0,  /**< Port 0 */
77#ifdef IX_NPE_MPHYMULTIPORT   
78#ifdef IX_NPE_HSS_MPHY4PORT
79    IX_UTOPIA_PORT_1,      /**< Port 1 */
80    IX_UTOPIA_PORT_2,      /**< Port 2 */
81    IX_UTOPIA_PORT_3,      /**< Port 3 */
82#else
83    IX_UTOPIA_PORT_1,      /**< Port 1 */
84    IX_UTOPIA_PORT_2,      /**< Port 2 */
85    IX_UTOPIA_PORT_3,      /**< Port 3 */
86    IX_UTOPIA_PORT_4,      /**< Port 4 */
87    IX_UTOPIA_PORT_5,      /**< Port 5 */
88    IX_UTOPIA_PORT_6,      /**< Port 6 */
89    IX_UTOPIA_PORT_7,      /**< Port 7 */
90    IX_UTOPIA_PORT_8,      /**< Port 8 */
91    IX_UTOPIA_PORT_9,      /**< Port 9 */
92    IX_UTOPIA_PORT_10,     /**< Port 10 */
93    IX_UTOPIA_PORT_11,     /**< Port 11 */
94#endif     
95#endif /* IX_NPE_MPHY */
96    IX_UTOPIA_MAX_PORTS    /**< Not a port - just a definition for the
97                           * maximum possible ports
98                           */
99} IxAtmLogicalPort;
100
101/**
102 * @def IX_ATM_CELL_PAYLOAD_SIZE
103 * @brief Size of a ATM cell payload
104 */
105#define IX_ATM_CELL_PAYLOAD_SIZE             (48)
106
107/**
108 * @def IX_ATM_CELL_SIZE
109 * @brief Size of a ATM cell, including header
110 */
111#define IX_ATM_CELL_SIZE                     (53)
112
113/**
114 * @def IX_ATM_CELL_SIZE_NO_HEC
115 * @brief Size of a ATM cell, excluding HEC byte
116 */
117#define IX_ATM_CELL_SIZE_NO_HEC              (IX_ATM_CELL_SIZE - 1)
118
119/**
120 * @def IX_ATM_OAM_CELL_SIZE_NO_HEC
121 * @brief Size of a OAM cell, excluding HEC byte
122 */
123#define IX_ATM_OAM_CELL_SIZE_NO_HEC          IX_ATM_CELL_SIZE_NO_HEC
124
125/**
126 * @def IX_ATM_AAL0_48_CELL_PAYLOAD_SIZE
127 * @brief Size of a AAL0 48 Cell payload
128 */
129#define IX_ATM_AAL0_48_CELL_PAYLOAD_SIZE     IX_ATM_CELL_PAYLOAD_SIZE
130
131/**
132 * @def IX_ATM_AAL5_CELL_PAYLOAD_SIZE
133 * @brief Size of a AAL5 Cell payload
134 */
135#define IX_ATM_AAL5_CELL_PAYLOAD_SIZE        IX_ATM_CELL_PAYLOAD_SIZE
136
137/**
138 * @def IX_ATM_AAL0_52_CELL_SIZE_NO_HEC
139 * @brief Size of a AAL0 52 Cell, excluding HEC byte
140 */
141#define IX_ATM_AAL0_52_CELL_SIZE_NO_HEC      IX_ATM_CELL_SIZE_NO_HEC
142
143
144/**
145 * @def IX_ATM_MAX_VPI
146 * @brief Maximum value of an ATM VPI
147 */
148#define IX_ATM_MAX_VPI 255
149
150/**
151 * @def IX_ATM_MAX_VCI
152 * @brief Maximum value of an ATM VCI
153 */
154#define IX_ATM_MAX_VCI 65535
155
156 /**
157 * @def IX_ATM_MAX_NUM_AAL_VCS
158 * @brief Maximum number of active AAL5/AAL0 VCs in the system
159 */
160#define IX_ATM_MAX_NUM_AAL_VCS 32
161
162/**
163 * @def IX_ATM_MAX_NUM_VC
164 * @brief Maximum number of active AAL5/AAL0 VCs in the system
165 * The use of this macro is depreciated, it is retained for
166 * backward compatiblity. For current software release
167 * and beyond the define IX_ATM_MAX_NUM_AAL_VC should be used.
168 */
169#define IX_ATM_MAX_NUM_VC IX_ATM_MAX_NUM_AAL_VCS
170
171
172
173/**
174 * @def IX_ATM_MAX_NUM_OAM_TX_VCS
175 * @brief Maximum number of active OAM Tx VCs in the system,
176 *        1 OAM VC per port
177 */
178#define IX_ATM_MAX_NUM_OAM_TX_VCS IX_UTOPIA_MAX_PORTS
179
180/**
181 * @def IX_ATM_MAX_NUM_OAM_RX_VCS
182 * @brief Maximum number of active OAM Rx VCs in the system,
183 *        1 OAM VC shared accross all ports
184 */
185#define IX_ATM_MAX_NUM_OAM_RX_VCS 1
186
187/**
188 * @def IX_ATM_MAX_NUM_AAL_OAM_TX_VCS
189 * @brief Maximum number of active AAL5/AAL0/OAM Tx VCs in the system
190 */
191#define IX_ATM_MAX_NUM_AAL_OAM_TX_VCS (IX_ATM_MAX_NUM_AAL_VCS + IX_ATM_MAX_NUM_OAM_TX_VCS)
192
193/**
194 * @def IX_ATM_MAX_NUM_AAL_OAM_RX_VCS
195 * @brief Maximum number of active AAL5/AAL0/OAM Rx VCs in the system
196 */
197#define IX_ATM_MAX_NUM_AAL_OAM_RX_VCS (IX_ATM_MAX_NUM_AAL_VCS + IX_ATM_MAX_NUM_OAM_RX_VCS)
198
199/**
200 *  @def IX_ATM_IDLE_CELLS_CONNID
201 *  @brief VC Id used to indicate idle cells in the returned schedule table.
202 */
203#define IX_ATM_IDLE_CELLS_CONNID 0
204
205
206/**
207 *  @def IX_ATM_CELL_HEADER_VCI_GET
208 *  @brief get the VCI field from a cell header
209 */
210#define IX_ATM_CELL_HEADER_VCI_GET(cellHeader) \
211    (((cellHeader) >> 4) & IX_OAM_VCI_BITS_MASK);
212
213/**
214 *  @def IX_ATM_CELL_HEADER_VPI_GET
215 *  @brief get the VPI field from a cell header
216 */
217#define IX_ATM_CELL_HEADER_VPI_GET(cellHeader) \
218    (((cellHeader) >> 20) & IX_OAM_VPI_BITS_MASK);
219
220/**
221 *  @def IX_ATM_CELL_HEADER_PTI_GET
222 *  @brief get the PTI field from a cell header
223 */
224#define IX_ATM_CELL_HEADER_PTI_GET(cellHeader) \
225    ((cellHeader) >> 1) & IX_OAM_PTI_BITS_MASK;
226
227/**
228 * @typedef IxAtmCellHeader
229 *
230 * @brief ATM Cell Header, does not contain 4 byte HEC, added by NPE-A
231 */
232typedef unsigned int IxAtmCellHeader;
233
234
235/**
236 * @enum IxAtmServiceCategory
237 *
238 * @brief Enumerated type representing available ATM service categories.
239 *   For more informatoin on these categories, see "Traffic Management
240 *   Specification" v4.1, published by the ATM Forum -
241 *   http://www.atmforum.com
242 */
243typedef enum
244{
245    IX_ATM_CBR,    /**< Constant Bit Rate */
246    IX_ATM_RTVBR,  /**< Real Time Variable Bit Rate */
247    IX_ATM_VBR,    /**< Variable Bit Rate */
248    IX_ATM_UBR,    /**< Unspecified Bit Rate */
249    IX_ATM_ABR     /**< Available Bit Rate (not supported) */
250
251} IxAtmServiceCategory;
252
253/**
254 *
255 * @enum IxAtmRxQueueId
256 *
257 * @brief Rx Queue Type for RX traffic
258 *
259 * IxAtmRxQueueId defines the queues involved for receiving data.
260 *
261 * There are two queues to facilitate prioritisation handling
262 * and processing the 2 queues with different algorithms and
263 * constraints
264 *
265 * e.g. : one queue can carry voice (or time-critical traffic), the
266 * other queue can carry non-voice traffic
267 *
268 */
269typedef enum
270{
271    IX_ATM_RX_A = 0,      /**< RX queue A */
272    IX_ATM_RX_B,          /**< RX queue B */
273    IX_ATM_MAX_RX_STREAMS /**< Maximum number of RX streams */
274} IxAtmRxQueueId;
275
276/**
277 * @brief Structure describing an ATM traffic contract for a Virtual
278 *         Connection (VC).
279 *
280 * Structure is used to specify the requested traffic contract for a
281 * VC to the IxAtmSch component using the @ref ixAtmSchVcModelSetup
282 * interface.
283 *
284 * These parameters are defined by the ATM forum working group
285 * (http://www.atmforum.com).
286 *
287 * @note Typical values for a voice channel 64 Kbit/s
288 * - atmService @a IX_ATM_RTVBR
289 * - pcr   400  (include IP overhead, and AAL5 trailer)
290 * - cdvt  5000000 (5 ms)
291 * - scr = pcr
292 *
293 * @note Typical values for a data channel 800 Kbit/s
294 * - atmService @a IX_ATM_UBR
295 * - pcr   1962  (include IP overhead, and AAL5 trailer)
296 * - cdvt  5000000 (5 ms)
297 *
298 */
299typedef struct
300{
301    IxAtmServiceCategory atmService; /**< ATM service category */
302    UINT64 pcr;   /**< Peak Cell Rate - cells per second */
303    UINT64 cdvt;  /**< Cell Delay Variation Tolerance - in nanoseconds */
304    UINT64 scr;   /**< Sustained Cell Rate - cells per second */
305    UINT64 mbs;   /**< Max Burst Size - cells */
306    UINT64 mcr;   /**< Minimum Cell Rate - cells per second */
307    UINT64 mfs;   /**< Max Frame Size - cells */
308} IxAtmTrafficDescriptor;
309
310/**
311 * @typedef IxAtmConnId
312 *
313 * @brief ATM VC data connection identifier.
314 *
315 * This is is generated by IxAtmdAcc when a successful connection is
316 * made on a VC. The is the ID by which IxAtmdAcc knows an active
317 * VC and should be used in IxAtmdAcc API calls to reference a
318 * specific VC.
319 */
320typedef unsigned int IxAtmConnId;
321
322/**
323 * @typedef IxAtmSchedulerVcId
324 *
325 * @brief ATM VC scheduling connection identifier.
326 *
327 * This id is generated and used by ATM Tx controller, generally
328 * the traffic shaper (e.g. IxAtmSch). The IxAtmdAcc component
329 * will request one of these Ids whenever a data connection on
330 * a Tx VC is requested. This ID will be used in callbacks to
331 * the ATM Transmission Ctrl s/w (e.g. IxAtmm) to reference a
332 * particular VC.
333 */
334typedef int IxAtmSchedulerVcId;
335
336/**
337 * @typedef IxAtmNpeRxVcId
338 *
339 * @brief ATM Rx VC identifier used by the ATM Npe.
340 *
341 * This Id is generated by IxAtmdAcc when a successful data connection
342 * is made on a rx VC.
343 */
344typedef unsigned int IxAtmNpeRxVcId;
345
346/**
347 * @brief ATM Schedule Table entry
348 *
349 * This IxAtmScheduleTableEntry is used by an ATM scheduler to inform
350 * IxAtmdAcc about the data to transmit (in term of cells per VC)
351 *
352 * This structure defines
353 * @li the number of cells to be transmitted (numberOfCells)
354 * @li the VC connection to be used for transmission (connId).
355 *
356 * @note - When the connection Id value is IX_ATM_IDLE_CELLS_CONNID, the
357 * corresponding number of idle cells will be transmitted to the hardware.
358 *
359 */
360typedef struct
361{
362    IxAtmConnId connId; /**< connection Id
363                 *
364                 * Identifier of VC from which cells are to be transmitted.
365                 * When this valus is IX_ATM_IDLE_CELLS_CONNID, this indicates
366                 * that the system should transmit the specified number
367                 * of idle cells. Unknown connIds result in the transmission
368                 * idle cells.
369                 */
370    unsigned int numberOfCells; /**< number of cells to transmit
371                 *
372                 * The number of contiguous cells to schedule from this VC
373                 * at this point. The valid range is from 1 to
374                 * @a IX_ATM_SCHEDULETABLE_MAXCELLS_PER_ENTRY. This
375                 * number can swap over mbufs and pdus. OverSchduling results
376                 * in the transmission of idle cells.
377                 */
378} IxAtmScheduleTableEntry;
379
380/**
381 * @brief This structure defines a schedule table which gives details
382 *         on which data (from which VCs) should be transmitted for a
383 *         forthcoming period of time for a particular port and the
384 *         order in which that data should be transmitted.
385 *
386 *  The schedule table consists of a series of entries each of which
387 *  will schedule one or more cells from a particular registered VC.
388 *  The total number of cells scheduled and the total number of
389 *  entries in the table are also indicated.
390 *
391 */
392typedef struct
393{
394    unsigned tableSize;      /**< Number of entries
395                              *
396                              * Indicates the total number of
397                              *   entries in the table.
398                              */
399    unsigned totalCellSlots; /**< Number of cells
400                              *
401                              * Indicates the total number of ATM
402                              *   cells which are scheduled by all the
403                              *   entries in the table.
404                              */
405    IxAtmScheduleTableEntry *table; /**< Pointer to schedule entries
406                                     *
407                                     * Pointer to an array
408                                     *   containing tableSize entries
409                                     */
410} IxAtmScheduleTable;
411
412#endif /* IXATMTYPES_H */
413
414/**
415 * @} defgroup IxAtmTypes
416 */
417
418
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