source: SVN/cambria/redboot/packages/devs/eth/intel/npe/common/current/include/IxQueueAssignments.h @ 1

Last change on this file since 1 was 1, checked in by Tim Harvey, 2 years ago

restored latest version of files from server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 17.9 KB
Line 
1/**
2 * @file IxQueueAssignments.h
3 *
4 * @author Intel Corporation
5 * @date 29-Oct-2004
6 *
7 * @brief Central definition for queue assignments
8 *
9 * Design Notes:
10 * This file contains queue assignments used by Ethernet (EthAcc),
11 * HSS (HssAcc), ATM (atmdAcc) and DMA (dmaAcc) access libraries.
12 *
13 * Note: Ethernet QoS traffic class definitions are managed separately
14 * by EthDB in IxEthDBQoS.h.
15 *
16 * @par
17 * IXP400 SW Release version 2.3
18 *
19 * -- Copyright Notice --
20 *
21 * @par
22 * Copyright (c) 2001-2005, Intel Corporation.
23 * All rights reserved.
24 *
25 * @par
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions
28 * are met:
29 * 1. Redistributions of source code must retain the above copyright
30 *    notice, this list of conditions and the following disclaimer.
31 * 2. Redistributions in binary form must reproduce the above copyright
32 *    notice, this list of conditions and the following disclaimer in the
33 *    documentation and/or other materials provided with the distribution.
34 * 3. Neither the name of the Intel Corporation nor the names of its contributors
35 *    may be used to endorse or promote products derived from this software
36 *    without specific prior written permission.
37 *
38 *
39 * @par
40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
41 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
50 * SUCH DAMAGE.
51 *
52 *
53 * @par
54 * -- End of Copyright Notice --
55 */
56/* ------------------------------------------------------
57   Doxygen group definitions
58   ------------------------------------------------------ */
59/**
60 * @defgroup IxQueueAssignments Intel (R) IXP400 Software Queue Assignments
61 *
62 * @brief Queue Assignments used by Ethernet, HSS, ATM and DMA access libraries. Ethernet QoS traffic class definitions are mapped by EthDB in IxEthDBQoS.h
63 *
64 */ 
65
66#ifndef IxQueueAssignments_H
67#define IxQueueAssignments_H
68
69#if defined(__ixp42X) || defined(__ixp46X) || defined(__ixp43X)
70#include "IxQMgr.h"
71#endif /* __ixp42X */
72
73/***************************************************************************
74 *  Queue assignments for ATM
75 ***************************************************************************/
76
77/**
78 * @ingroup IxQueueAssignments
79 *
80 * @def IX_NPE_MPHYMULTIPORT
81 *
82 * @brief Global compiler switch to select between 3 possible NPE Modes
83 * Define this macro to enable MPHY mode
84 *
85 * Default(No Switch) = MultiPHY Utopia2
86 * IX_UTOPIAMODE = 1 for single Phy Utopia1
87 * IX_MPHYSINGLEPORT = 1 for single Phy Utopia2
88 */
89#define IX_NPE_MPHYMULTIPORT 1
90#if IX_UTOPIAMODE == 1
91#undef  IX_NPE_MPHYMULTIPORT
92#endif
93#if IX_MPHYSINGLEPORT == 1
94#undef  IX_NPE_MPHYMULTIPORT
95#endif
96
97/**
98 *
99 * @ingroup IxQueueAssignments
100 *
101 * @def IX_NPE_A_TXDONE_QUEUE_HIGHWATERMARK
102 *
103 * @brief The NPE reserves the High Watermark for its operation. But it must be set by the Xscale
104 */
105#define IX_NPE_A_TXDONE_QUEUE_HIGHWATERMARK  2
106
107/**
108 *
109 * @ingroup IxQueueAssignments
110 *
111 * @def IX_NPE_A_QMQ_ATM_TX_DONE
112 *
113 * @brief Queue ID for ATM Transmit Done queue
114 */
115#define IX_NPE_A_QMQ_ATM_TX_DONE       IX_QMGR_QUEUE_1
116
117/**
118 *
119 * @ingroup IxQueueAssignments
120 *
121 * @def IX_NPE_A_QMQ_ATM_TX0
122 *
123 * @brief Queue ID for ATM transmit Queue in a single phy configuration
124 */
125#define IX_NPE_A_QMQ_ATM_TX0           IX_QMGR_QUEUE_2
126
127
128/**
129 *
130 * @ingroup IxQueueAssignments
131 *
132 * @def IX_NPE_A_QMQ_ATM_TXID_MIN
133 *
134 * @brief Queue Manager Queue ID for ATM transmit Queue with minimum number of queue
135 *
136 */
137
138/**
139 *
140 * @ingroup IxQueueAssignments
141 *
142 * @def IX_NPE_A_QMQ_ATM_TXID_MAX
143 *
144 * @brief Queue Manager Queue ID for ATM transmit Queue with maximum number of queue
145 *
146 */
147
148/**
149 *
150 * @ingroup IxQueueAssignments
151 *
152 * @def IX_NPE_A_QMQ_ATM_RX_HI
153 *
154 * @brief Queue Manager Queue ID for ATM Receive high Queue
155 *
156 */
157
158/**
159 *
160 * @ingroup IxQueueAssignments
161 *
162 * @def IX_NPE_A_QMQ_ATM_RX_LO
163 *
164 * @brief Queue Manager Queue ID for ATM Receive low Queue
165 */
166
167#ifdef IX_NPE_MPHYMULTIPORT
168/**
169 *
170 * @ingroup IxQueueAssignments
171 *
172 * @def IX_NPE_A_QMQ_ATM_TX1
173 *
174 * @brief Queue ID for ATM transmit Queue Multiphy from 1 to 11
175 */
176#define IX_NPE_A_QMQ_ATM_TX1           IX_NPE_A_QMQ_ATM_TX0+1
177#define IX_NPE_A_QMQ_ATM_TX2           IX_NPE_A_QMQ_ATM_TX1+1
178#define IX_NPE_A_QMQ_ATM_TX3           IX_NPE_A_QMQ_ATM_TX2+1
179#define IX_NPE_A_QMQ_ATM_TX4           IX_NPE_A_QMQ_ATM_TX3+1
180#define IX_NPE_A_QMQ_ATM_TX5           IX_NPE_A_QMQ_ATM_TX4+1
181#define IX_NPE_A_QMQ_ATM_TX6           IX_NPE_A_QMQ_ATM_TX5+1
182#define IX_NPE_A_QMQ_ATM_TX7           IX_NPE_A_QMQ_ATM_TX6+1
183#define IX_NPE_A_QMQ_ATM_TX8           IX_NPE_A_QMQ_ATM_TX7+1
184#define IX_NPE_A_QMQ_ATM_TX9           IX_NPE_A_QMQ_ATM_TX8+1
185#define IX_NPE_A_QMQ_ATM_TX10          IX_NPE_A_QMQ_ATM_TX9+1
186#define IX_NPE_A_QMQ_ATM_TX11          IX_NPE_A_QMQ_ATM_TX10+1
187#define IX_NPE_A_QMQ_ATM_TXID_MIN      IX_NPE_A_QMQ_ATM_TX0
188#define IX_NPE_A_QMQ_ATM_TXID_MAX      IX_NPE_A_QMQ_ATM_TX11
189#define IX_NPE_A_QMQ_ATM_RX_HI         IX_QMGR_QUEUE_21
190#define IX_NPE_A_QMQ_ATM_RX_LO         IX_QMGR_QUEUE_22
191#else
192#define IX_NPE_A_QMQ_ATM_TXID_MIN      IX_NPE_A_QMQ_ATM_TX0
193#define IX_NPE_A_QMQ_ATM_TXID_MAX      IX_NPE_A_QMQ_ATM_TX0
194#define IX_NPE_A_QMQ_ATM_RX_HI         IX_QMGR_QUEUE_10
195#define IX_NPE_A_QMQ_ATM_RX_LO         IX_QMGR_QUEUE_11
196#endif /* MPHY */
197
198/**
199 *
200 * @ingroup IxQueueAssignments
201 *
202 * @def IX_NPE_A_QMQ_ATM_FREE_VC0
203 *
204 * @brief Hardware QMgr Queue ID for ATM Free VC Queue.
205 *
206 * There are 32 Hardware QMgr Queue ID; from IX_NPE_A_QMQ_ATM_FREE_VC1 to
207 * IX_NPE_A_QMQ_ATM_FREE_VC30
208 */
209#define IX_NPE_A_QMQ_ATM_FREE_VC0      IX_QMGR_QUEUE_32
210#define IX_NPE_A_QMQ_ATM_FREE_VC1      IX_NPE_A_QMQ_ATM_FREE_VC0+1
211#define IX_NPE_A_QMQ_ATM_FREE_VC2      IX_NPE_A_QMQ_ATM_FREE_VC1+1
212#define IX_NPE_A_QMQ_ATM_FREE_VC3      IX_NPE_A_QMQ_ATM_FREE_VC2+1
213#define IX_NPE_A_QMQ_ATM_FREE_VC4      IX_NPE_A_QMQ_ATM_FREE_VC3+1
214#define IX_NPE_A_QMQ_ATM_FREE_VC5      IX_NPE_A_QMQ_ATM_FREE_VC4+1
215#define IX_NPE_A_QMQ_ATM_FREE_VC6      IX_NPE_A_QMQ_ATM_FREE_VC5+1
216#define IX_NPE_A_QMQ_ATM_FREE_VC7      IX_NPE_A_QMQ_ATM_FREE_VC6+1
217#define IX_NPE_A_QMQ_ATM_FREE_VC8      IX_NPE_A_QMQ_ATM_FREE_VC7+1
218#define IX_NPE_A_QMQ_ATM_FREE_VC9      IX_NPE_A_QMQ_ATM_FREE_VC8+1
219#define IX_NPE_A_QMQ_ATM_FREE_VC10     IX_NPE_A_QMQ_ATM_FREE_VC9+1
220#define IX_NPE_A_QMQ_ATM_FREE_VC11     IX_NPE_A_QMQ_ATM_FREE_VC10+1
221#define IX_NPE_A_QMQ_ATM_FREE_VC12     IX_NPE_A_QMQ_ATM_FREE_VC11+1
222#define IX_NPE_A_QMQ_ATM_FREE_VC13     IX_NPE_A_QMQ_ATM_FREE_VC12+1
223#define IX_NPE_A_QMQ_ATM_FREE_VC14     IX_NPE_A_QMQ_ATM_FREE_VC13+1
224#define IX_NPE_A_QMQ_ATM_FREE_VC15     IX_NPE_A_QMQ_ATM_FREE_VC14+1
225#define IX_NPE_A_QMQ_ATM_FREE_VC16     IX_NPE_A_QMQ_ATM_FREE_VC15+1
226#define IX_NPE_A_QMQ_ATM_FREE_VC17     IX_NPE_A_QMQ_ATM_FREE_VC16+1
227#define IX_NPE_A_QMQ_ATM_FREE_VC18     IX_NPE_A_QMQ_ATM_FREE_VC17+1
228#define IX_NPE_A_QMQ_ATM_FREE_VC19     IX_NPE_A_QMQ_ATM_FREE_VC18+1
229#define IX_NPE_A_QMQ_ATM_FREE_VC20     IX_NPE_A_QMQ_ATM_FREE_VC19+1
230#define IX_NPE_A_QMQ_ATM_FREE_VC21     IX_NPE_A_QMQ_ATM_FREE_VC20+1
231#define IX_NPE_A_QMQ_ATM_FREE_VC22     IX_NPE_A_QMQ_ATM_FREE_VC21+1
232#define IX_NPE_A_QMQ_ATM_FREE_VC23     IX_NPE_A_QMQ_ATM_FREE_VC22+1
233#define IX_NPE_A_QMQ_ATM_FREE_VC24     IX_NPE_A_QMQ_ATM_FREE_VC23+1
234#define IX_NPE_A_QMQ_ATM_FREE_VC25     IX_NPE_A_QMQ_ATM_FREE_VC24+1
235#define IX_NPE_A_QMQ_ATM_FREE_VC26     IX_NPE_A_QMQ_ATM_FREE_VC25+1
236#define IX_NPE_A_QMQ_ATM_FREE_VC27     IX_NPE_A_QMQ_ATM_FREE_VC26+1
237#define IX_NPE_A_QMQ_ATM_FREE_VC28     IX_NPE_A_QMQ_ATM_FREE_VC27+1
238#define IX_NPE_A_QMQ_ATM_FREE_VC29     IX_NPE_A_QMQ_ATM_FREE_VC28+1
239#define IX_NPE_A_QMQ_ATM_FREE_VC30     IX_NPE_A_QMQ_ATM_FREE_VC29+1
240#define IX_NPE_A_QMQ_ATM_FREE_VC31     IX_NPE_A_QMQ_ATM_FREE_VC30+1
241
242/**
243 *
244 * @ingroup IxQueueAssignments
245 *
246 * @def IX_NPE_A_QMQ_ATM_RXFREE_MIN
247 *
248 * @brief The minimum queue ID for FreeVC queue
249 */
250#define IX_NPE_A_QMQ_ATM_RXFREE_MIN  IX_NPE_A_QMQ_ATM_FREE_VC0
251
252/**
253 * @def IX_NPE_A_QMQ_ATM_RXFREE_MAX
254 *
255 * @brief The maximum queue ID for FreeVC queue
256 */
257#define IX_NPE_A_QMQ_ATM_RXFREE_MAX  IX_NPE_A_QMQ_ATM_FREE_VC31
258
259/**
260 *
261 * @ingroup IxQueueAssignments
262 *
263 * @def IX_NPE_A_QMQ_OAM_FREE_VC
264 * @brief OAM Rx Free queue ID
265 */
266#ifdef IX_NPE_MPHYMULTIPORT
267#define IX_NPE_A_QMQ_OAM_FREE_VC       IX_QMGR_QUEUE_14
268#else
269#define IX_NPE_A_QMQ_OAM_FREE_VC       IX_QMGR_QUEUE_3
270#endif /* MPHY */
271
272/****************************************************************************
273 * Queue assignments for HSS
274 ****************************************************************************/
275
276#ifndef IX_NPE_HSS_MPHY4PORT
277/****  HSS Port 0 ****/
278
279/**
280 *
281 * @ingroup IxQueueAssignments
282 *
283 * @def IX_NPE_A_QMQ_HSS0_CHL_RX_TRIG
284 *
285 * @brief Hardware QMgr Queue ID for HSS Port 0 Channelized Receive trigger
286 */
287#define IX_NPE_A_QMQ_HSS0_CHL_RX_TRIG   IX_QMGR_QUEUE_12
288
289#else
290/****  HSS Port 0 ****/
291
292/**
293 *
294 * @ingroup IxQueueAssignments
295 *
296 * @def IX_NPE_A_QMQ_HSS0_CHL_RX_TRIG
297 *
298 * @brief Hardware QMgr Queue ID for HSS Port 0 Channelized Receive trigger
299 */
300#define IX_NPE_A_QMQ_HSS0_CHL_RX_TRIG   IX_QMGR_QUEUE_20
301
302#endif
303
304/**
305 *
306 * @ingroup IxQueueAssignments
307 *
308 * @def IX_NPE_A_QMQ_HSS0_PKT_RX
309 *
310 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive
311 */
312#define IX_NPE_A_QMQ_HSS0_PKT_RX        IX_QMGR_QUEUE_13
313
314/**
315 *
316 * @ingroup IxQueueAssignments
317 *
318 * @def IX_NPE_A_QMQ_HSS0_PKT_TX0
319 *
320 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 0
321 */
322#define IX_NPE_A_QMQ_HSS0_PKT_TX0       IX_QMGR_QUEUE_14
323
324/**
325 *
326 * @ingroup IxQueueAssignments
327 *
328 * @def IX_NPE_A_QMQ_HSS0_PKT_TX1
329 *
330 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 1
331 */
332#define IX_NPE_A_QMQ_HSS0_PKT_TX1       IX_QMGR_QUEUE_15
333
334/**
335 *
336 * @ingroup IxQueueAssignments
337 *
338 * @def IX_NPE_A_QMQ_HSS0_PKT_TX2
339 *
340 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 2
341 */
342#define IX_NPE_A_QMQ_HSS0_PKT_TX2       IX_QMGR_QUEUE_16
343
344/**
345 *
346 * @ingroup IxQueueAssignments
347 *
348 * @def IX_NPE_A_QMQ_HSS0_PKT_TX3
349 *
350 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 3
351 */
352#define IX_NPE_A_QMQ_HSS0_PKT_TX3       IX_QMGR_QUEUE_17
353
354/**
355 *
356 * @ingroup IxQueueAssignments
357 *
358 * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE0
359 *
360 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 0
361 */
362#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE0  IX_QMGR_QUEUE_18
363
364/**
365 *
366 * @ingroup IxQueueAssignments
367 *
368 * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE1
369 *
370 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 1
371 */
372#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE1  IX_QMGR_QUEUE_19
373
374/**
375 *
376 * @ingroup IxQueueAssignments
377 *
378 * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE2
379 *
380 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 2
381 */
382#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE2  IX_QMGR_QUEUE_20
383
384/**
385 *
386 * @ingroup IxQueueAssignments
387 *
388 * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE3
389 *
390 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 3
391 */
392#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE3  IX_QMGR_QUEUE_21
393
394/**
395 *
396 * @ingroup IxQueueAssignments
397 *
398 * @def IX_NPE_A_QMQ_HSS0_PKT_TX_DONE
399 *
400 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit Done queue
401 */
402#define IX_NPE_A_QMQ_HSS0_PKT_TX_DONE   IX_QMGR_QUEUE_22
403
404/****  HSS Port 1 ****/
405
406/**
407 *
408 * @ingroup IxQueueAssignments
409 *
410 * @def IX_NPE_A_QMQ_HSS1_CHL_RX_TRIG
411 *
412 * @brief Hardware QMgr Queue ID for HSS Port 1 Channelized Receive trigger
413 */
414#define IX_NPE_A_QMQ_HSS1_CHL_RX_TRIG   IX_QMGR_QUEUE_10
415
416/**
417 *
418 * @ingroup IxQueueAssignments
419 *
420 * @def IX_NPE_A_QMQ_HSS1_PKT_RX
421 *
422 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive
423 */
424#define IX_NPE_A_QMQ_HSS1_PKT_RX        IX_QMGR_QUEUE_0
425
426/**
427 *
428 * @ingroup IxQueueAssignments
429 *
430 * @def IX_NPE_A_QMQ_HSS1_PKT_TX0
431 *
432 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 0
433 */
434#define IX_NPE_A_QMQ_HSS1_PKT_TX0       IX_QMGR_QUEUE_5
435
436/**
437 *
438 * @ingroup IxQueueAssignments
439 *
440 * @def IX_NPE_A_QMQ_HSS1_PKT_TX1
441 *
442 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 1
443 */
444#define IX_NPE_A_QMQ_HSS1_PKT_TX1       IX_QMGR_QUEUE_6
445
446/**
447 *
448 * @ingroup IxQueueAssignments
449 *
450 * @def IX_NPE_A_QMQ_HSS1_PKT_TX2
451 *
452 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 2
453 */
454#define IX_NPE_A_QMQ_HSS1_PKT_TX2       IX_QMGR_QUEUE_7
455
456/**
457 *
458 * @ingroup IxQueueAssignments
459 *
460 * @def IX_NPE_A_QMQ_HSS1_PKT_TX3
461 *
462 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 3
463 */
464#define IX_NPE_A_QMQ_HSS1_PKT_TX3       IX_QMGR_QUEUE_8
465
466/**
467 *
468 * @ingroup IxQueueAssignments
469 *
470 * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE0
471 *
472 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 0
473 */
474#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE0  IX_QMGR_QUEUE_1
475
476/**
477 *
478 * @ingroup IxQueueAssignments
479 *
480 * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE1
481 *
482 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 1
483 */
484#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE1  IX_QMGR_QUEUE_2
485
486/**
487 *
488 * @ingroup IxQueueAssignments
489 *
490 * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE2
491 *
492 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 2
493 */
494#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE2  IX_QMGR_QUEUE_3
495
496/**
497 *
498 * @ingroup IxQueueAssignments
499 *
500 * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE3
501 *
502 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 3
503 */
504#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE3  IX_QMGR_QUEUE_4
505
506/**
507 *
508 * @ingroup IxQueueAssignments
509 *
510 * @def IX_NPE_A_QMQ_HSS1_PKT_TX_DONE
511 *
512 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit Done queue
513 */
514#define IX_NPE_A_QMQ_HSS1_PKT_TX_DONE   IX_QMGR_QUEUE_9
515
516/*****************************************************************************************
517 * Queue assignments for DMA
518 *****************************************************************************************/
519
520#define IX_DMA_NPE_A_REQUEST_QID IX_QMGR_QUEUE_19   /**< Queue Id for NPE A DMA Request */
521#define IX_DMA_NPE_A_DONE_QID    IX_QMGR_QUEUE_20   /**< Queue Id for NPE A DMA Done    */
522#define IX_DMA_NPE_B_REQUEST_QID IX_QMGR_QUEUE_24   /**< Queue Id for NPE B DMA Request */
523#define IX_DMA_NPE_B_DONE_QID    IX_QMGR_QUEUE_26   /**< Queue Id for NPE B DMA Done    */
524#define IX_DMA_NPE_C_REQUEST_QID IX_QMGR_QUEUE_25   /**< Queue Id for NPE C DMA Request */
525#define IX_DMA_NPE_C_DONE_QID    IX_QMGR_QUEUE_27   /**< Queue Id for NPE C DMA Done    */
526
527
528#if defined(__ixp42X) || defined(__ixp46X) || defined(__ixp43X)
529/*****************************************************************************************
530 * Queue assignments for Ethernet
531 *
532 * Note: Rx queue definitions, which include QoS traffic class definitions
533 * are managed by EthDB and declared in IxEthDBQoS.h.
534 *
535 * Note: NPEB RxFree queues have 3 possible configurations setup in EthAcc:
536 *  1. Single port using Queue 27 only (default)
537 *  2. Four ports using Queues { 0, 1, 2, 3}
538 *  3. Four ports using Queues {26,27,29,30}
539 *****************************************************************************************/
540
541/**
542*
543* @ingroup IxQueueAssignments
544*
545* @def IX_ETH_ACC_RX_FREE_NPEA_Q
546*
547* @brief Supply Rx Buffers Ethernet Q for NPEA
548*
549*/
550#define IX_ETH_ACC_RX_FREE_NPEA_Q    (IX_QMGR_QUEUE_26)
551
552/**
553*
554* @ingroup IxQueueAssignments
555*
556* @def IX_ETH_ACC_RX_FREE_NPEB_Q
557*
558* @brief Supply Rx Buffers Ethernet Q for NPEB (for single port images only)
559*
560*/
561#define IX_ETH_ACC_RX_FREE_NPEB_Q    (IX_QMGR_QUEUE_27)
562
563/**
564*
565* @ingroup IxQueueAssignments
566*
567* @def IX_ETH_ACC_RX_FREE_NPEC_Q
568*
569* @brief Supply Rx Buffers Ethernet Q for NPEC
570*
571*/
572#define IX_ETH_ACC_RX_FREE_NPEC_Q    (IX_QMGR_QUEUE_28)
573
574/**
575*
576* @ingroup IxQueueAssignments
577*
578* @def IX_ETH_ACC_TX_NPEA_Q
579*
580* @brief Submit frame Q for NPEA
581*
582*/
583#define IX_ETH_ACC_TX_NPEA_Q    (IX_QMGR_QUEUE_23)
584
585
586/**
587*
588* @ingroup IxQueueAssignments
589*
590* @def IX_ETH_ACC_TX_NPEB_Q
591*
592* @brief Submit frame Q for NPEB
593*
594*/
595#define IX_ETH_ACC_TX_NPEB_Q    (IX_QMGR_QUEUE_24)
596
597/**
598*
599* @ingroup IxQueueAssignments
600*
601* @def IX_ETH_ACC_TX_NPEC_Q
602*
603* @brief Submit frame Q for NPEC
604*
605*/
606#define IX_ETH_ACC_TX_NPEC_Q    (IX_QMGR_QUEUE_25)
607
608/**
609*
610* @ingroup IxQueueAssignments
611*
612* @def IX_ETH_ACC_TX_DONE_Q
613*
614* @brief Transmit complete Q for all NPEs
615*
616*/
617#define IX_ETH_ACC_TX_DONE_Q    (IX_QMGR_QUEUE_31)
618
619#endif /* __ixp42X */
620
621/*****************************************************************************************
622 * Queue assignments for Crypto
623 *****************************************************************************************/
624
625/** Crypto Service Request Queue */
626#define IX_CRYPTO_ACC_CRYPTO_REQ_Q  (IX_QMGR_QUEUE_29)
627
628/** Crypto Service Done Queue */
629#define IX_CRYPTO_ACC_CRYPTO_DONE_Q (IX_QMGR_QUEUE_30)
630
631/** Crypto Req Q CB tag */
632#define IX_CRYPTO_ACC_CRYPTO_REQ_Q_CB_TAG   (0)
633
634/** Crypto Done Q CB tag */
635#define IX_CRYPTO_ACC_CRYPTO_DONE_Q_CB_TAG  (1)
636
637/** WEP Service Request Queue */
638#define IX_CRYPTO_ACC_WEP_REQ_Q  (IX_QMGR_QUEUE_21)
639
640/** WEP Service Done Queue */
641#define IX_CRYPTO_ACC_WEP_DONE_Q (IX_QMGR_QUEUE_22)
642
643/** WEP Req Q CB tag */
644#define IX_CRYPTO_ACC_WEP_REQ_Q_CB_TAG      (2)
645
646/** WEP Done Q CB tag */
647#define IX_CRYPTO_ACC_WEP_DONE_Q_CB_TAG     (3)
648
649/** Number of queues allocate to crypto hardware accelerator services */
650#define IX_CRYPTO_ACC_NUM_OF_CRYPTO_Q       (2)
651
652/** Number of queues allocate to WEP NPE services */
653#define IX_CRYPTO_ACC_NUM_OF_WEP_NPE_Q      (2)
654                                                     
655/** Number of queues allocate to CryptoAcc component */
656#define IX_CRYPTO_ACC_NUM_OF_Q (IX_CRYPTO_ACC_NUM_OF_CRYPTO_Q + IX_CRYPTO_ACC_NUM_OF_WEP_NPE_Q)   
657
658#endif /* IxQueueAssignments_H */
Note: See TracBrowser for help on using the repository browser.