source: SVN/cambria/redboot/packages/devs/eth/intel/npe/common/current/include/osal/modules/ioMem/IxOsalMemAccess.h @ 1

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1/**
2 * @file IxOsalMemAccess.h
3 *
4 * @brief Header file for memory access
5 *
6 * @par
7 * @version $Revision: 1.1.2.2 $
8 *
9 * @par
10 * IXP400 SW Release version  2.0
11 *
12 * -- Intel Copyright Notice --
13 *
14 * @par
15 * Copyright 2002-2005 Intel Corporation All Rights Reserved.
16 *
17 * @par
18 * The source code contained or described herein and all documents
19 * related to the source code ("Material") are owned by Intel Corporation
20 * or its suppliers or licensors.  Title to the Material remains with
21 * Intel Corporation or its suppliers and licensors.
22 *
23 * @par
24 * The Material is protected by worldwide copyright and trade secret laws
25 * and treaty provisions. No part of the Material may be used, copied,
26 * reproduced, modified, published, uploaded, posted, transmitted,
27 * distributed, or disclosed in any way except in accordance with the
28 * applicable license agreement .
29 *
30 * @par
31 * No license under any patent, copyright, trade secret or other
32 * intellectual property right is granted to or conferred upon you by
33 * disclosure or delivery of the Materials, either expressly, by
34 * implication, inducement, estoppel, except in accordance with the
35 * applicable license agreement.
36 *
37 * @par
38 * Unless otherwise agreed by Intel in writing, you may not remove or
39 * alter this notice or any other notice embedded in Materials by Intel
40 * or Intel's suppliers or licensors in any way.
41 *
42 * @par
43 * For further details, please see the file README.TXT distributed with
44 * this software.
45 *
46 * @par
47 * -- End Intel Copyright Notice --
48 */
49
50#ifndef IxOsalMemAccess_H
51#define IxOsalMemAccess_H
52
53
54/* Global BE switch
55 *
56 *  Should be set only in BE mode and only if the component uses I/O memory.
57 */
58
59#if defined (__BIG_ENDIAN)
60
61#define IX_OSAL_BE_MAPPING
62
63#endif /* Global switch */
64
65
66/* By default only static memory maps in use;
67   define IX_OSAL_DYNAMIC_MEMORY_MAP per component if dynamic maps are
68   used instead in that component */
69#define IX_OSAL_STATIC_MEMORY_MAP
70
71
72/*
73 * SDRAM coherency mode
74 * Must be defined to BE, LE_DATA_COHERENT or LE_ADDRESS_COHERENT.
75 * The mode changes depending on OS
76 */
77#if defined (IX_OSAL_LINUX_BE) || defined (IX_OSAL_VXWORKS_BE) || defined (IX_OSAL_ECOS_BE)
78
79#define IX_SDRAM_BE
80
81#elif defined (IX_OSAL_VXWORKS_LE)
82
83#define IX_SDRAM_LE_DATA_COHERENT
84
85#elif defined (IX_OSAL_LINUX_LE)
86
87#define IX_SDRAM_LE_DATA_COHERENT
88
89#elif defined (IX_OSAL_WINCE_LE)
90
91#define IX_SDRAM_LE_DATA_COHERENT
92
93#elif defined (IX_OSAL_EBOOT_LE)
94
95#define IX_SDRAM_LE_ADDRESS_COHERENT
96
97#elif defined (IX_OSAL_ECOS_LE)
98
99#define IX_SDRAM_BE
100
101#endif
102
103
104
105
106/**************************************
107 * Retrieve current component mapping *
108 **************************************/
109
110/*
111 * Only use customized mapping for LE.
112 *
113 */
114#if defined (IX_OSAL_VXWORKS_LE) || defined (IX_OSAL_LINUX_LE) || defined (IX_OSAL_WINCE_LE) || defined (IX_OSAL_EBOOT_LE) || defined (IX_OSAL_ECOS_LE)
115
116#include "IxOsalOsIxp400CustomizedMapping.h"
117
118#endif
119
120
121/*******************************************************************
122 * Turn off IX_STATIC_MEMORY map for components using dynamic maps *
123 *******************************************************************/
124#ifdef IX_OSAL_DYNAMIC_MEMORY_MAP
125
126#undef IX_OSAL_STATIC_MEMORY_MAP
127
128#endif
129
130
131/************************************************************
132 * Turn off BE access for components using LE or no mapping *
133 ************************************************************/
134
135#if ( defined (IX_OSAL_LE_AC_MAPPING) || defined (IX_OSAL_LE_DC_MAPPING) || defined (IX_OSAL_NO_MAPPING) )
136
137#undef IX_OSAL_BE_MAPPING
138
139#endif
140
141
142/*****************
143 * Safety checks *
144 *****************/
145
146/* Default to no_mapping */
147#if !defined (IX_OSAL_BE_MAPPING) && !defined (IX_OSAL_LE_AC_MAPPING) && !defined (IX_OSAL_LE_DC_MAPPING) && !defined (IX_OSAL_NO_MAPPING)
148
149#define IX_OSAL_NO_MAPPING
150
151#endif /* check at least one mapping */
152
153/* No more than one mapping can be defined for a component */
154#if   (defined (IX_OSAL_BE_MAPPING)    && defined (IX_OSAL_LE_AC_MAPPING))  \
155    ||(defined (IX_OSAL_BE_MAPPING)    && defined (IX_OSAL_LE_DC_MAPPING))  \
156    ||(defined (IX_OSAL_BE_MAPPING)    && defined (IX_OSAL_NO_MAPPING))     \
157    ||(defined (IX_OSAL_LE_DC_MAPPING) && defined (IX_OSAL_NO_MAPPING))     \
158    ||(defined (IX_OSAL_LE_DC_MAPPING) && defined (IX_OSAL_LE_AC_MAPPING))      \
159    ||(defined (IX_OSAL_LE_AC_MAPPING) && defined (IX_OSAL_NO_MAPPING))
160
161
162#ifdef IX_OSAL_BE_MAPPING
163#warning IX_OSAL_BE_MAPPING is defined
164#endif
165
166#ifdef IX_OSAL_LE_AC_MAPPING
167#warning IX_OSAL_LE_AC_MAPPING is defined
168#endif
169
170#ifdef IX_OSAL_LE_DC_MAPPING
171#warning IX_OSAL_LE_DC_MAPPING is defined
172#endif
173
174#ifdef IX_OSAL_NO_MAPPING
175#warning IX_OSAL_NO_MAPPING is defined
176#endif
177
178#error More than one I/O mapping is defined, please check your component mapping
179
180#endif /* check at most one mapping */
181
182
183/* Now set IX_OSAL_COMPONENT_MAPPING */
184
185#ifdef IX_OSAL_BE_MAPPING
186#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_BE
187#endif
188
189#ifdef IX_OSAL_LE_AC_MAPPING
190#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE_AC
191#endif
192
193#ifdef IX_OSAL_LE_DC_MAPPING
194#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE_DC
195#endif
196
197#ifdef IX_OSAL_NO_MAPPING
198#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE
199#endif
200
201
202/* SDRAM coherency should be defined */
203#if !defined (IX_SDRAM_BE) && !defined (IX_SDRAM_LE_DATA_COHERENT) && !defined (IX_SDRAM_LE_ADDRESS_COHERENT)
204
205#error SDRAM coherency must be defined
206
207#endif /* SDRAM coherency must be defined */
208
209/* SDRAM coherency cannot be defined in several ways */
210#if (defined (IX_SDRAM_BE) && (defined (IX_SDRAM_LE_DATA_COHERENT) || defined (IX_SDRAM_LE_ADDRESS_COHERENT))) \
211    || (defined (IX_SDRAM_LE_DATA_COHERENT) && (defined (IX_SDRAM_BE) || defined (IX_SDRAM_LE_ADDRESS_COHERENT))) \
212    || (defined (IX_SDRAM_LE_ADDRESS_COHERENT) && (defined (IX_SDRAM_BE) || defined (IX_SDRAM_LE_DATA_COHERENT)))
213
214#error SDRAM coherency cannot be defined in more than one way
215
216#endif /* SDRAM coherency must be defined exactly once */
217
218
219/*********************
220 * Read/write macros *
221 *********************/
222
223/* WARNING - except for addition of special cookie read/write macros (see below)
224             these macros are NOT user serviceable. Please do not modify */
225
226#define IX_OSAL_READ_LONG_RAW(wAddr)          (*(wAddr))
227#define IX_OSAL_READ_SHORT_RAW(sAddr)         (*(sAddr))
228#define IX_OSAL_READ_BYTE_RAW(bAddr)          (*(bAddr))
229#define IX_OSAL_WRITE_LONG_RAW(wAddr, wData)  (*(wAddr) = (wData))
230#define IX_OSAL_WRITE_SHORT_RAW(sAddr,sData)  (*(sAddr) = (sData))
231#define IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)  (*(bAddr) = (bData))
232
233#ifdef __linux
234
235/* Linux - specific cookie reads/writes.
236  Redefine per OS if dynamic memory maps are used
237  and I/O memory is accessed via functions instead of raw pointer access. */
238
239#define IX_OSAL_READ_LONG_COOKIE(wCookie)           (readl((UINT32) (wCookie) ))
240#define IX_OSAL_READ_SHORT_COOKIE(sCookie)          (readw((UINT32) (sCookie) ))
241#define IX_OSAL_READ_BYTE_COOKIE(bCookie)           (readb((UINT32) (bCookie) ))
242#define IX_OSAL_WRITE_LONG_COOKIE(wCookie, wData)   (writel(wData, (UINT32) (wCookie) ))
243#define IX_OSAL_WRITE_SHORT_COOKIE(sCookie, sData)  (writew(sData, (UINT32) (sCookie) ))
244#define IX_OSAL_WRITE_BYTE_COOKIE(bCookie, bData)   (writeb(bData, (UINT32) (bCookie) ))
245
246#endif /* linux */
247
248#ifdef __wince
249
250/* WinCE - specific cookie reads/writes. */
251
252static __inline__ UINT32
253ixOsalWinCEReadLCookie (volatile UINT32 * lCookie)
254{
255    return *lCookie;
256}
257
258static __inline__ UINT16
259ixOsalWinCEReadWCookie (volatile UINT16 * wCookie)
260{
261#if 0
262    UINT32 auxVal = *((volatile UINT32 *) wCookie);
263    if ((unsigned) wCookie & 3)
264        return (UINT16) (auxVal >> 16);
265    else
266        return (UINT16) (auxVal & 0xffff);
267#else
268    return *wCookie;
269#endif
270}
271
272static __inline__ UINT8
273ixOsalWinCEReadBCookie (volatile UINT8 * bCookie)
274{
275#if 0
276    UINT32 auxVal = *((volatile UINT32 *) bCookie);
277    return (UINT8) ((auxVal >> (3 - (((unsigned) bCookie & 3) << 3)) & 0xff));
278#else
279    return *bCookie;
280#endif
281}
282
283static __inline__ void
284ixOsalWinCEWriteLCookie (volatile UINT32 * lCookie, UINT32 lVal)
285{
286    *lCookie = lVal;
287}
288
289static __inline__ void
290ixOsalWinCEWriteWCookie (volatile UINT16 * wCookie, UINT16 wVal)
291{
292#if 0
293    volatile UINT32 *auxCookie =
294        (volatile UINT32 *) ((unsigned) wCookie & ~3);
295    if ((unsigned) wCookie & 3)
296    {
297        *auxCookie &= 0xffff;
298        *auxCookie |= (UINT32) wVal << 16;
299    }
300    else
301    {
302        *auxCookie &= ~0xffff;
303        *auxCookie |= (UINT32) wVal & 0xffff;
304    }
305#else
306    *wCookie = wVal;
307#endif
308}
309
310static __inline__ void
311ixOsalWinCEWriteBCookie (volatile UINT8 * bCookie, UINT8 bVal)
312{
313#if 0
314    volatile UINT32 *auxCookie =
315        (volatile UINT32 *) ((unsigned) bCookie & ~3);
316    *auxCookie &= 0xff << (3 - (((unsigned) bCookie & 3) << 3));
317    *auxCookie |= (UINT32) bVal << (3 - (((unsigned) bCookie & 3) << 3));
318#else
319    *bCookie = bVal;
320#endif
321}
322
323
324#define IX_OSAL_READ_LONG_COOKIE(wCookie)           (ixOsalWinCEReadLCookie(wCookie))
325#define IX_OSAL_READ_SHORT_COOKIE(sCookie)          (ixOsalWinCEReadWCookie(sCookie))
326#define IX_OSAL_READ_BYTE_COOKIE(bCookie)           (ixOsalWinCEReadBCookie(bCookie))
327#define IX_OSAL_WRITE_LONG_COOKIE(wCookie, wData)   (ixOsalWinCEWriteLCookie(wCookie, wData))
328#define IX_OSAL_WRITE_SHORT_COOKIE(sCookie, sData)  (ixOsalWinCEWriteWCookie(sCookie, sData))
329#define IX_OSAL_WRITE_BYTE_COOKIE(bCookie, bData)   (ixOsalWinCEWriteBCookie(bCookie, bData))
330
331#endif /* wince */
332
333#if defined (__vxworks) || defined (__ECOS) || \
334    (defined (__linux) && defined (IX_OSAL_STATIC_MEMORY_MAP)) || \
335    (defined (__wince) && defined (IX_OSAL_STATIC_MEMORY_MAP))
336
337#define IX_OSAL_READ_LONG_IO(wAddr)            IX_OSAL_READ_LONG_RAW(wAddr)
338#define IX_OSAL_READ_SHORT_IO(sAddr)           IX_OSAL_READ_SHORT_RAW(sAddr)
339#define IX_OSAL_READ_BYTE_IO(bAddr)            IX_OSAL_READ_BYTE_RAW(bAddr)
340#define IX_OSAL_WRITE_LONG_IO(wAddr, wData)    IX_OSAL_WRITE_LONG_RAW(wAddr, wData)
341#define IX_OSAL_WRITE_SHORT_IO(sAddr, sData)   IX_OSAL_WRITE_SHORT_RAW(sAddr, sData)
342#define IX_OSAL_WRITE_BYTE_IO(bAddr, bData)    IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)
343
344#elif (defined (__linux) && !defined (IX_OSAL_STATIC_MEMORY_MAP)) || \
345      (defined (__wince) && !defined (IX_OSAL_STATIC_MEMORY_MAP))
346
347#ifndef __wince
348#include <asm/io.h>
349#endif /* ndef __wince */
350
351#define IX_OSAL_READ_LONG_IO(wAddr)            IX_OSAL_READ_LONG_COOKIE(wAddr)
352#define IX_OSAL_READ_SHORT_IO(sAddr)           IX_OSAL_READ_SHORT_COOKIE(sAddr)
353#define IX_OSAL_READ_BYTE_IO(bAddr)            IX_OSAL_READ_BYTE_COOKIE(bAddr)
354#define IX_OSAL_WRITE_LONG_IO(wAddr, wData)    IX_OSAL_WRITE_LONG_COOKIE(wAddr, wData)
355#define IX_OSAL_WRITE_SHORT_IO(sAddr, sData)   IX_OSAL_WRITE_SHORT_COOKIE(sAddr, sData)
356#define IX_OSAL_WRITE_BYTE_IO(bAddr, bData)    IX_OSAL_WRITE_BYTE_COOKIE(bAddr, bData)
357
358#endif
359
360/* Define BE macros */
361#define IX_OSAL_READ_LONG_BE(wAddr)          IX_OSAL_BE_BUSTOXSL(IX_OSAL_READ_LONG_IO((volatile UINT32 *) (wAddr) ))
362#define IX_OSAL_READ_SHORT_BE(sAddr)         IX_OSAL_BE_BUSTOXSS(IX_OSAL_READ_SHORT_IO((volatile UINT16 *) (sAddr) ))
363#define IX_OSAL_READ_BYTE_BE(bAddr)          IX_OSAL_BE_BUSTOXSB(IX_OSAL_READ_BYTE_IO((volatile UINT8 *) (bAddr) ))
364#define IX_OSAL_WRITE_LONG_BE(wAddr, wData)  IX_OSAL_WRITE_LONG_IO((volatile UINT32 *) (wAddr), IX_OSAL_BE_XSTOBUSL((UINT32) (wData) ))
365#define IX_OSAL_WRITE_SHORT_BE(sAddr, sData) IX_OSAL_WRITE_SHORT_IO((volatile UINT16 *) (sAddr), IX_OSAL_BE_XSTOBUSS((UINT16) (sData) ))
366#define IX_OSAL_WRITE_BYTE_BE(bAddr, bData)  IX_OSAL_WRITE_BYTE_IO((volatile UINT8 *) (bAddr), IX_OSAL_BE_XSTOBUSB((UINT8) (bData) ))
367
368/* Define LE AC macros */
369#define IX_OSAL_READ_LONG_LE_AC(wAddr)          IX_OSAL_READ_LONG_IO((volatile UINT32 *) IX_OSAL_LE_AC_BUSTOXSL((UINT32) (wAddr) ))
370#define IX_OSAL_READ_SHORT_LE_AC(sAddr)         IX_OSAL_READ_SHORT_IO((volatile UINT16 *) IX_OSAL_LE_AC_BUSTOXSS((UINT32) (sAddr) ))
371#define IX_OSAL_READ_BYTE_LE_AC(bAddr)          IX_OSAL_READ_BYTE_IO((volatile UINT8 *) IX_OSAL_LE_AC_BUSTOXSB((UINT32) (bAddr) ))
372#define IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData)  IX_OSAL_WRITE_LONG_IO((volatile UINT32 *) IX_OSAL_LE_AC_XSTOBUSL((UINT32) (wAddr) ), (UINT32) (wData))
373#define IX_OSAL_WRITE_SHORT_LE_AC(sAddr, sData) IX_OSAL_WRITE_SHORT_IO((volatile UINT16 *) IX_OSAL_LE_AC_XSTOBUSS((UINT32) (sAddr) ), (UINT16) (sData))
374#define IX_OSAL_WRITE_BYTE_LE_AC(bAddr, bData)  IX_OSAL_WRITE_BYTE_IO((volatile UINT8 *) IX_OSAL_LE_AC_XSTOBUSB((UINT32) (bAddr) ), (UINT8) (bData))
375
376
377/* Inline functions are required here to avoid reading the same I/O location 2 or 4 times for the byte swap */
378static __inline__ UINT32
379ixOsalDataCoherentLongReadSwap (volatile UINT32 * wAddr)
380{
381    UINT32 wData = IX_OSAL_READ_LONG_IO (wAddr);
382    return IX_OSAL_LE_DC_BUSTOXSL (wData);
383}
384
385static __inline__ UINT16
386ixOsalDataCoherentShortReadSwap (volatile UINT16 * sAddr)
387{
388    UINT16 sData = IX_OSAL_READ_SHORT_IO (sAddr);
389    return IX_OSAL_LE_DC_BUSTOXSS (sData);
390}
391
392static __inline__ void
393ixOsalDataCoherentLongWriteSwap (volatile UINT32 * wAddr, UINT32 wData)
394{
395    wData = IX_OSAL_LE_DC_XSTOBUSL (wData);
396    IX_OSAL_WRITE_LONG_IO (wAddr, wData);
397}
398
399static __inline__ void
400ixOsalDataCoherentShortWriteSwap (volatile UINT16 * sAddr, UINT16 sData)
401{
402    sData = IX_OSAL_LE_DC_XSTOBUSS (sData);
403    IX_OSAL_WRITE_SHORT_IO (sAddr, sData);
404}
405
406/* Define LE DC macros */
407
408#define IX_OSAL_READ_LONG_LE_DC(wAddr)          ixOsalDataCoherentLongReadSwap((volatile UINT32 *) (wAddr) )
409#define IX_OSAL_READ_SHORT_LE_DC(sAddr)         ixOsalDataCoherentShortReadSwap((volatile UINT16 *) (sAddr) )
410#define IX_OSAL_READ_BYTE_LE_DC(bAddr)          IX_OSAL_LE_DC_BUSTOXSB(IX_OSAL_READ_BYTE_IO((volatile UINT8 *) (bAddr) ))
411#define IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData)  ixOsalDataCoherentLongWriteSwap((volatile UINT32 *) (wAddr), (UINT32) (wData))
412#define IX_OSAL_WRITE_SHORT_LE_DC(sAddr, sData) ixOsalDataCoherentShortWriteSwap((volatile UINT16 *) (sAddr), (UINT16) (sData))
413#define IX_OSAL_WRITE_BYTE_LE_DC(bAddr, bData)  IX_OSAL_WRITE_BYTE_IO((volatile UINT8 *) (bAddr), IX_OSAL_LE_DC_XSTOBUSB((UINT8) (bData)))
414
415#if defined (IX_OSAL_BE_MAPPING)
416
417#define IX_OSAL_READ_LONG(wAddr)            IX_OSAL_READ_LONG_BE(wAddr)
418#define IX_OSAL_READ_SHORT(sAddr)               IX_OSAL_READ_SHORT_BE(sAddr)
419#define IX_OSAL_READ_BYTE(bAddr)                IX_OSAL_READ_BYTE_BE(bAddr)
420#define IX_OSAL_WRITE_LONG(wAddr, wData)        IX_OSAL_WRITE_LONG_BE(wAddr, wData)
421#define IX_OSAL_WRITE_SHORT(sAddr, sData)       IX_OSAL_WRITE_SHORT_BE(sAddr, sData)
422#define IX_OSAL_WRITE_BYTE(bAddr, bData)        IX_OSAL_WRITE_BYTE_BE(bAddr, bData)
423
424#elif defined (IX_OSAL_LE_AC_MAPPING)
425
426#define IX_OSAL_READ_LONG(wAddr)            IX_OSAL_READ_LONG_LE_AC(wAddr)
427#define IX_OSAL_READ_SHORT(sAddr)               IX_OSAL_READ_SHORT_LE_AC(sAddr)
428#define IX_OSAL_READ_BYTE(bAddr)                IX_OSAL_READ_BYTE_LE_AC(bAddr)
429#define IX_OSAL_WRITE_LONG(wAddr, wData)        IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData)
430#define IX_OSAL_WRITE_SHORT(sAddr, sData)       IX_OSAL_WRITE_SHORT_LE_AC(sAddr, sData)
431#define IX_OSAL_WRITE_BYTE(bAddr, bData)        IX_OSAL_WRITE_BYTE_LE_AC(bAddr, bData)
432
433#elif defined (IX_OSAL_LE_DC_MAPPING)
434
435#define IX_OSAL_READ_LONG(wAddr)            IX_OSAL_READ_LONG_LE_DC(wAddr)
436#define IX_OSAL_READ_SHORT(sAddr)               IX_OSAL_READ_SHORT_LE_DC(sAddr)
437#define IX_OSAL_READ_BYTE(bAddr)                IX_OSAL_READ_BYTE_LE_DC(bAddr)
438#define IX_OSAL_WRITE_LONG(wAddr, wData)        IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData)
439#define IX_OSAL_WRITE_SHORT(sAddr, sData)       IX_OSAL_WRITE_SHORT_LE_DC(sAddr, sData)
440#define IX_OSAL_WRITE_BYTE(bAddr, bData)        IX_OSAL_WRITE_BYTE_LE_DC(bAddr, bData)
441
442#endif   /* End of BE and LE coherency mode switch */
443
444
445/* Reads/writes to and from memory shared with NPEs - depends on the SDRAM coherency */
446
447#if defined (IX_SDRAM_BE)
448
449#define IX_OSAL_READ_BE_SHARED_LONG(wAddr)            IX_OSAL_READ_LONG_RAW(wAddr)
450#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr)           IX_OSAL_READ_SHORT_RAW(sAddr)
451#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr)            IX_OSAL_READ_BYTE_RAW(bAddr)
452
453#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData)    IX_OSAL_WRITE_LONG_RAW(wAddr, wData)
454#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData)   IX_OSAL_WRITE_SHORT_RAW(sAddr, sData)
455#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData)    IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)
456
457#define IX_OSAL_SWAP_BE_SHARED_LONG(wData)            (wData)
458#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData)           (sData)
459#define IX_OSAL_SWAP_BE_SHARED_BYTE(bData)            (bData)
460
461#elif defined (IX_SDRAM_LE_ADDRESS_COHERENT)
462
463#define IX_OSAL_READ_BE_SHARED_LONG(wAddr)            IX_OSAL_READ_LONG_RAW(wAddr)
464#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr)           IX_OSAL_READ_SHORT_RAW(IX_OSAL_SWAP_SHORT_ADDRESS(sAddr))
465#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr)            IX_OSAL_READ_BYTE_RAW(IX_OSAL_SWAP_BYTE_ADDRESS(bAddr))
466
467#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData)    IX_OSAL_WRITE_LONG_RAW(wAddr, wData)
468#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData)   IX_OSAL_WRITE_SHORT_RAW(IX_OSAL_SWAP_SHORT_ADDRESS(sAddr), sData)
469#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData)    IX_OSAL_WRITE_BYTE_RAW(IX_OSAL_SWAP_BYTE_ADDRESS(bAddr), bData)
470
471#define IX_OSAL_SWAP_BE_SHARED_LONG(wData)            (wData)
472#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData)           (sData)
473#define IX_OSAL_SWAP_BE_SHARED_BYTE(bData)            (bData)
474
475#elif defined (IX_SDRAM_LE_DATA_COHERENT)
476
477#define IX_OSAL_READ_BE_SHARED_LONG(wAddr)            IX_OSAL_SWAP_LONG(IX_OSAL_READ_LONG_RAW(wAddr))
478#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr)           IX_OSAL_SWAP_SHORT(IX_OSAL_READ_SHORT_RAW(sAddr))
479#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr)            IX_OSAL_READ_BYTE_RAW(bAddr)
480
481#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData)    IX_OSAL_WRITE_LONG_RAW(wAddr, IX_OSAL_SWAP_LONG(wData))
482#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData)   IX_OSAL_WRITE_SHORT_RAW(sAddr, IX_OSAL_SWAP_SHORT(sData))
483#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData)    IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)
484
485#define IX_OSAL_SWAP_BE_SHARED_LONG(wData)            IX_OSAL_SWAP_LONG(wData)
486#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData)           IX_OSAL_SWAP_SHORT(sData)
487
488#endif
489
490
491#define IX_OSAL_COPY_BE_SHARED_LONG_ARRAY(wDestAddr, wSrcAddr, wCount) \
492  { \
493    UINT32 i; \
494    \
495    for ( i = 0 ; i < wCount ; i++ ) \
496    { \
497      * (((UINT32 *) wDestAddr) + i) = IX_OSAL_READ_BE_SHARED_LONG(((UINT32 *) wSrcAddr) + i); \
498    }; \
499  };
500
501#endif /* IxOsalMemAccess_H */
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