source: SVN/cambria/redboot/packages/devs/eth/intel/npe/npeMh/current/include/IxNpeMhMacros_p.h @ 1

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1/**
2 * @file IxNpeMhMacros_p.h
3 *
4 * @author Intel Corporation
5 * @date 21 Jan 2002
6 *
7 * @brief This file contains the macros for the IxNpeMh component.
8 *
9 *
10 * @par
11 * IXP400 SW Release version 2.3
12 *
13 * -- Copyright Notice --
14 *
15 * @par
16 * Copyright (c) 2001-2005, Intel Corporation.
17 * All rights reserved.
18 *
19 * @par
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 * 1. Redistributions of source code must retain the above copyright
24 *    notice, this list of conditions and the following disclaimer.
25 * 2. Redistributions in binary form must reproduce the above copyright
26 *    notice, this list of conditions and the following disclaimer in the
27 *    documentation and/or other materials provided with the distribution.
28 * 3. Neither the name of the Intel Corporation nor the names of its contributors
29 *    may be used to endorse or promote products derived from this software
30 *    without specific prior written permission.
31 *
32 *
33 * @par
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
35 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
36 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
37 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
38 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
39 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
40 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
41 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
42 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
43 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
44 * SUCH DAMAGE.
45 *
46 *
47 * @par
48 * -- End of Copyright Notice --
49*/
50
51/**
52 * @defgroup IxNpeMhMacros_p IxNpeMhMacros_p
53 *
54 * @brief Macros for the IxNpeMh component.
55 *
56 * @{
57 */
58
59#ifndef IXNPEMHMACROS_P_H
60#define IXNPEMHMACROS_P_H
61
62/* if we are running as a unit test */
63#ifdef IX_UNIT_TEST
64#undef NDEBUG
65#endif /* #ifdef IX_UNIT_TEST */
66
67#include "IxOsal.h"
68
69/*
70 * #defines for function return types, etc.
71 */
72
73#define IX_NPEMH_SHOW_TEXT_WIDTH (40) /**< text width for stats display */
74#define IX_NPEMH_SHOW_STAT_WIDTH (10) /**< stat width for stats display */
75
76/**
77 * @def IX_NPEMH_SHOW
78 *
79 * @brief Macro for displaying a stat preceded by a textual description.
80 */
81
82#define IX_NPEMH_SHOW(TEXT, STAT) \
83    ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, \
84               "%-40s: %10d\n", (int) TEXT, (int) STAT, 0, 0, 0, 0)
85
86/*
87 * Prototypes for interface functions.
88 */
89
90/**
91 * @typedef IxNpeMhTraceTypes
92 *
93 * @brief Enumeration defining IxNpeMh trace levels
94 */
95
96typedef enum
97{
98    IX_NPEMH_TRACE_OFF     = IX_OSAL_LOG_LVL_NONE,    /**< no trace */
99    IX_NPEMH_WARNING       = IX_OSAL_LOG_LVL_WARNING, /**< warning */
100    IX_NPEMH_DEBUG         = IX_OSAL_LOG_LVL_MESSAGE, /**< debug */
101    IX_NPEMH_FN_ENTRY_EXIT = IX_OSAL_LOG_LVL_DEBUG3   /**< function entry/exit */
102} IxNpeMhTraceTypes;
103
104#ifdef IX_UNIT_TEST
105#define IX_NPEMH_TRACE_LEVEL (IX_NPEMH_FN_ENTRY_EXIT) /**< trace level */
106#else
107#define IX_NPEMH_TRACE_LEVEL (IX_NPEMH_TRACE_OFF) /**< trace level */
108#endif
109
110/**
111 * @def IX_NPEMH_TRACE0
112 *
113 * @brief Trace macro taking 0 arguments.
114 */
115
116#define IX_NPEMH_TRACE0(LEVEL, STR) \
117    IX_NPEMH_TRACE6(LEVEL, STR, 0, 0, 0, 0, 0, 0)
118
119/**
120 * @def IX_NPEMH_TRACE1
121 *
122 * @brief Trace macro taking 1 argument.
123 */
124
125#define IX_NPEMH_TRACE1(LEVEL, STR, ARG1) \
126    IX_NPEMH_TRACE6(LEVEL, STR, ARG1, 0, 0, 0, 0, 0)
127
128/**
129 * @def IX_NPEMH_TRACE2
130 *
131 * @brief Trace macro taking 2 arguments.
132 */
133
134#define IX_NPEMH_TRACE2(LEVEL, STR, ARG1, ARG2) \
135    IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, 0, 0, 0, 0)
136
137/**
138 * @def IX_NPEMH_TRACE3
139 *
140 * @brief Trace macro taking 3 arguments.
141 */
142
143#define IX_NPEMH_TRACE3(LEVEL, STR, ARG1, ARG2, ARG3) \
144    IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, 0, 0, 0)
145
146/**
147 * @def IX_NPEMH_TRACE4
148 *
149 * @brief Trace macro taking 4 arguments.
150 */
151
152#define IX_NPEMH_TRACE4(LEVEL, STR, ARG1, ARG2, ARG3, ARG4) \
153    IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, 0, 0)
154
155/**
156 * @def IX_NPEMH_TRACE5
157 *
158 * @brief Trace macro taking 5 arguments.
159 */
160
161#define IX_NPEMH_TRACE5(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5) \
162    IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5, 0)
163
164/**
165 * @def IX_NPEMH_TRACE6
166 *
167 * @brief Trace macro taking 6 arguments.
168 */
169
170#define IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6) \
171{ \
172    if (LEVEL <= IX_NPEMH_TRACE_LEVEL) \
173    { \
174        (void) ixOsalLog (LEVEL, IX_OSAL_LOG_DEV_STDOUT, (STR), \
175                          (int)(ARG1), (int)(ARG2), (int)(ARG3), \
176                          (int)(ARG4), (int)(ARG5), (int)(ARG6)); \
177    } \
178}
179
180/**
181 * @def IX_NPEMH_ERROR_REPORT
182 *
183 * @brief Error reporting facility.
184 */
185
186#define IX_NPEMH_ERROR_REPORT(STR) \
187{ \
188    (void) ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, \
189                      (STR), 0, 0, 0, 0, 0, 0); \
190}
191
192/* if we are running on XScale, i.e. real environment */
193#if CPU==XSCALE
194
195/**
196 * @def IX_NPEMH_REGISTER_READ
197 *
198 * @brief This macro reads a memory-mapped register.
199 */
200
201#define IX_NPEMH_REGISTER_READ(registerAddress, value) \
202{ \
203    *value = IX_OSAL_READ_LONG(registerAddress); \
204}
205
206/**
207 * @def IX_NPEMH_REGISTER_READ_BITS
208 *
209 * @brief This macro partially reads a memory-mapped register.
210 */
211
212#define IX_NPEMH_REGISTER_READ_BITS(registerAddress, value, mask) \
213{ \
214    *value = (IX_OSAL_READ_LONG(registerAddress) & mask); \
215}
216
217/**
218 * @def IX_NPEMH_REGISTER_WRITE
219 *
220 * @brief This macro writes a memory-mapped register.
221 */
222
223#define IX_NPEMH_REGISTER_WRITE(registerAddress, value) \
224{ \
225    IX_OSAL_WRITE_LONG(registerAddress, value); \
226}
227
228/**
229 * @def IX_NPEMH_REGISTER_WRITE_BITS
230 *
231 * @brief This macro partially writes a memory-mapped register.
232 */
233
234#define IX_NPEMH_REGISTER_WRITE_BITS(registerAddress, value, mask) \
235{ \
236    UINT32 orig = IX_OSAL_READ_LONG(registerAddress); \
237    orig &= (~mask); \
238    orig |= (value & mask); \
239    IX_OSAL_WRITE_LONG(registerAddress, orig); \
240}
241
242
243/* if we are running as a unit test */
244#else /* #if CPU==XSCALE */
245
246#include "IxNpeMhTestRegister.h"
247
248/**
249 * @def IX_NPEMH_REGISTER_READ
250 *
251 * @brief This macro reads a memory-mapped register.
252 */
253
254#define IX_NPEMH_REGISTER_READ(registerAddress, value) \
255{ \
256    ixNpeMhTestRegisterRead (registerAddress, value); \
257}
258
259/**
260 * @def IX_NPEMH_REGISTER_READ_BITS
261 *
262 * @brief This macro partially reads a memory-mapped register.
263 */
264
265#define IX_NPEMH_REGISTER_READ_BITS(registerAddress, value, mask) \
266{ \
267    ixNpeMhTestRegisterReadBits (registerAddress, value, mask); \
268}
269
270/**
271 * @def IX_NPEMH_REGISTER_WRITE
272 *
273 * @brief This macro writes a memory-mapped register.
274 */
275
276#define IX_NPEMH_REGISTER_WRITE(registerAddress, value) \
277{ \
278    ixNpeMhTestRegisterWrite (registerAddress, value); \
279}
280
281/**
282 * @def IX_NPEMH_REGISTER_WRITE_BITS
283 *
284 * @brief This macro partially writes a memory-mapped register.
285 */
286
287#define IX_NPEMH_REGISTER_WRITE_BITS(registerAddress, value, mask) \
288{ \
289    ixNpeMhTestRegisterWriteBits (registerAddress, value, mask); \
290}
291
292#endif /* #if CPU==XSCALE */
293
294#endif /* IXNPEMHMACROS_P_H */
295
296/**
297 * @} defgroup IxNpeMhMacros_p
298 */
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