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1/**
2 * @file    IxQMgrAqmIf_p.h
3 *
4 * @author Intel Corporation
5 * @date    30-Oct-2001
6 *
7 * @brief   The IxQMgrAqmIf sub-component provides a number of inline
8 * functions for performing I/O on the AQM.
9 *
10 * Because  some functions contained in this module are inline and are
11 * used in other modules (within the QMgr component) the definitions are
12 * contained in this header file. The "normal" use of inline functions
13 * is to use the inline functions in the module in which they are
14 * defined. In this case these inline functions are used in external
15 * modules and therefore the use of "inline extern". What this means
16 * is as follows: if a function foo is declared as "inline extern"this
17 * definition is only used for inlining, in no case is the function
18 * compiled on its own. If the compiler cannot inline the function it
19 * becomes an external reference. Therefore in IxQMgrAqmIf.c all
20 * inline functions are defined without the "inline extern" specifier
21 * and so define the external references. In all other modules these
22 * funtions are defined as "inline extern".
23 *
24 *
25 * @par
26 * IXP400 SW Release version  2.0
27 *
28 * -- Intel Copyright Notice --
29 *
30 * @par
31 * Copyright 2002-2005 Intel Corporation All Rights Reserved.
32 *
33 * @par
34 * The source code contained or described herein and all documents
35 * related to the source code ("Material") are owned by Intel Corporation
36 * or its suppliers or licensors.  Title to the Material remains with
37 * Intel Corporation or its suppliers and licensors.
38 *
39 * @par
40 * The Material is protected by worldwide copyright and trade secret laws
41 * and treaty provisions. No part of the Material may be used, copied,
42 * reproduced, modified, published, uploaded, posted, transmitted,
43 * distributed, or disclosed in any way except in accordance with the
44 * applicable license agreement .
45 *
46 * @par
47 * No license under any patent, copyright, trade secret or other
48 * intellectual property right is granted to or conferred upon you by
49 * disclosure or delivery of the Materials, either expressly, by
50 * implication, inducement, estoppel, except in accordance with the
51 * applicable license agreement.
52 *
53 * @par
54 * Unless otherwise agreed by Intel in writing, you may not remove or
55 * alter this notice or any other notice embedded in Materials by Intel
56 * or Intel's suppliers or licensors in any way.
57 *
58 * @par
59 * For further details, please see the file README.TXT distributed with
60 * this software.
61 *
62 * @par
63 * -- End Intel Copyright Notice --
64*/
65
66#ifndef IXQMGRAQMIF_P_H
67#define IXQMGRAQMIF_P_H
68
69#include "IxOsalTypes.h"
70
71/*
72 * inline definition
73 */
74 
75#ifdef IX_OSAL_INLINE_ALL
76/* If IX_OSAL_INLINE_ALL is set then each inlineable API functions will be defined as
77   inline functions */
78#define IX_QMGR_AQMIF_INLINE IX_OSAL_INLINE_EXTERN
79#else   
80#ifdef IXQMGRAQMIF_C
81#ifndef IX_QMGR_AQMIF_INLINE
82#define IX_QMGR_AQMIF_INLINE
83#endif
84#else 
85#ifndef IX_QMGR_AQMIF_INLINE
86#define IX_QMGR_AQMIF_INLINE IX_OSAL_INLINE_EXTERN
87#endif
88#endif /* IXQMGRAQMIF_C */
89#endif /* IX_OSAL_INLINE */
90
91
92/*
93 * User defined include files.
94 */
95#include "IxQMgr.h"
96#include "IxQMgrLog_p.h"
97#include "IxQMgrQCfg_p.h"
98
99/* Because this file contains inline functions which will be compiled into
100 * other components, we need to ensure that the IX_COMPONENT_NAME define
101 * is set to ix_qmgr while this code is being compiled.  This will ensure
102 * that the correct implementation is provided for the memory access macros
103 * IX_OSAL_READ_LONG and IX_OSAL_WRITE_LONG which are used in this file.
104 * This must be done before including "IxOsalMemAccess.h"
105 */
106#define IX_QMGR_AQMIF_SAVED_COMPONENT_NAME IX_COMPONENT_NAME
107#undef  IX_COMPONENT_NAME
108#define IX_COMPONENT_NAME ix_qmgr
109#include "IxOsal.h"
110
111/*
112 * #defines and macros used in this file.
113 */
114
115/* Number of bytes per word */
116#define IX_QMGR_NUM_BYTES_PER_WORD 4
117
118/* Underflow bit mask  */
119#define IX_QMGR_UNDERFLOW_BIT_OFFSET    0x0
120
121/* Overflow bit mask */
122#define IX_QMGR_OVERFLOW_BIT_OFFSET     0x1
123
124/* Queue access register, queue 0 */
125#define IX_QMGR_QUEACC0_OFFSET      0x0000
126
127/* Size of queue access register in words */
128#define IX_QMGR_QUEACC_SIZE         0x4/*words*/
129
130/* Queue status register, queues 0-7 */
131#define IX_QMGR_QUELOWSTAT0_OFFSET  (IX_QMGR_QUEACC0_OFFSET +\
132(IX_QMGR_MAX_NUM_QUEUES * IX_QMGR_QUEACC_SIZE * IX_QMGR_NUM_BYTES_PER_WORD))
133
134/* Queue status register, queues 8-15 */
135#define IX_QMGR_QUELOWSTAT1_OFFSET  (IX_QMGR_QUELOWSTAT0_OFFSET +\
136                                     IX_QMGR_NUM_BYTES_PER_WORD)
137
138/* Queue status register, queues 16-23 */
139#define IX_QMGR_QUELOWSTAT2_OFFSET  (IX_QMGR_QUELOWSTAT1_OFFSET +\
140                                     IX_QMGR_NUM_BYTES_PER_WORD)
141
142/* Queue status register, queues 24-31 */
143#define IX_QMGR_QUELOWSTAT3_OFFSET  (IX_QMGR_QUELOWSTAT2_OFFSET +\
144                                     IX_QMGR_NUM_BYTES_PER_WORD)
145
146/* Queue status register Q status bits mask */
147#define IX_QMGR_QUELOWSTAT_QUE_STS_BITS_MASK 0xF
148
149/* Size of queue 0-31 status register */
150#define IX_QMGR_QUELOWSTAT_SIZE     0x4 /*words*/
151
152/* The number of queues' status specified per word */
153#define IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD 0x8
154
155/* Queue UF/OF status register queues 0-15  */
156#define IX_QMGR_QUEUOSTAT0_OFFSET   (IX_QMGR_QUELOWSTAT3_OFFSET +\
157                                     IX_QMGR_NUM_BYTES_PER_WORD)
158/* Queue UF/OF status register queues 16-31 */
159#define IX_QMGR_QUEUOSTAT1_OFFSET   (IX_QMGR_QUEUOSTAT0_OFFSET +\
160                                     IX_QMGR_NUM_BYTES_PER_WORD)
161
162/* The number of queues' underflow/overflow status specified per word */
163#define IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD 0x10
164
165/* Queue NE status register, queues 32-63   */
166#define IX_QMGR_QUEUPPSTAT0_OFFSET  (IX_QMGR_QUEUOSTAT1_OFFSET +\
167                                     IX_QMGR_NUM_BYTES_PER_WORD)
168
169/* Queue F status register, queues 32-63    */
170#define IX_QMGR_QUEUPPSTAT1_OFFSET  (IX_QMGR_QUEUPPSTAT0_OFFSET +\
171                                     IX_QMGR_NUM_BYTES_PER_WORD)
172
173/* Size of queue 32-63 status register */
174#define IX_QMGR_QUEUPPSTAT_SIZE     0x2 /*words*/
175
176/* The number of queues' status specified per word */
177#define IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD 0x20
178
179/* Queue INT source select register, queues 0-7   */
180#define IX_QMGR_INT0SRCSELREG0_OFFSET (IX_QMGR_QUEUPPSTAT1_OFFSET   +\
181                                       IX_QMGR_NUM_BYTES_PER_WORD)
182
183/* Queue INT source select register, queues 8-15  */
184#define IX_QMGR_INT0SRCSELREG1_OFFSET (IX_QMGR_INT0SRCSELREG0_OFFSET+\
185                                       IX_QMGR_NUM_BYTES_PER_WORD)
186
187/* Queue INT source select register, queues 16-23 */
188#define IX_QMGR_INT0SRCSELREG2_OFFSET (IX_QMGR_INT0SRCSELREG1_OFFSET+\
189                                       IX_QMGR_NUM_BYTES_PER_WORD)
190
191/* Queue INT source select register, queues 24-31 */
192#define IX_QMGR_INT0SRCSELREG3_OFFSET (IX_QMGR_INT0SRCSELREG2_OFFSET+\
193                                       IX_QMGR_NUM_BYTES_PER_WORD)
194
195/* Size of interrupt source select reegister */
196#define IX_QMGR_INT0SRCSELREG_SIZE  0x4 /*words*/
197
198/* The number of queues' interrupt source select specified per word*/
199#define IX_QMGR_INTSRC_NUM_QUE_PER_WORD 0x8
200
201/* Queue INT enable register, queues 0-31  */
202#define IX_QMGR_QUEIEREG0_OFFSET    (IX_QMGR_INT0SRCSELREG3_OFFSET +\
203                                     IX_QMGR_NUM_BYTES_PER_WORD)
204
205/* Queue INT enable register, queues 32-63 */
206#define IX_QMGR_QUEIEREG1_OFFSET    (IX_QMGR_QUEIEREG0_OFFSET      +\
207                                     IX_QMGR_NUM_BYTES_PER_WORD)
208
209/* Queue INT register, queues 0-31  */
210#define IX_QMGR_QINTREG0_OFFSET     (IX_QMGR_QUEIEREG1_OFFSET +\
211                                     IX_QMGR_NUM_BYTES_PER_WORD)
212
213/* Queue INT register, queues 32-63 */
214#define IX_QMGR_QINTREG1_OFFSET     (IX_QMGR_QINTREG0_OFFSET  +\
215                                     IX_QMGR_NUM_BYTES_PER_WORD)
216
217/* Size of interrupt register */
218#define IX_QMGR_QINTREG_SIZE        0x2 /*words*/
219
220/* Number of queues' status specified per word */
221#define IX_QMGR_QINTREG_NUM_QUE_PER_WORD 0x20
222
223/* Number of bits per queue interrupt status */
224#define IX_QMGR_QINTREG_BITS_PER_QUEUE 0x1
225#define IX_QMGR_QINTREG_BIT_OFFSET 0x1
226
227/* Size of address space not used by AQM */
228#define IX_QMGR_AQM_UNUSED_ADDRESS_SPACE_SIZE_IN_BYTES  0x1bC0
229
230/* Queue config register, queue 0 */
231#define IX_QMGR_QUECONFIG_BASE_OFFSET (IX_QMGR_QINTREG1_OFFSET +\
232                             IX_QMGR_NUM_BYTES_PER_WORD +\
233                             IX_QMGR_AQM_UNUSED_ADDRESS_SPACE_SIZE_IN_BYTES)
234
235/* Total size of configuration words */
236#define IX_QMGR_QUECONFIG_SIZE      0x100
237
238/* Start of SRAM queue buffer space */
239#define IX_QMGR_QUEBUFFER_SPACE_OFFSET (IX_QMGR_QUECONFIG_BASE_OFFSET +\
240                                 IX_QMGR_MAX_NUM_QUEUES * IX_QMGR_NUM_BYTES_PER_WORD)
241
242/* Total bits in a word */
243#define BITS_PER_WORD 32
244
245/* Size of queue buffer space */
246#define IX_QMGR_QUE_BUFFER_SPACE_SIZE 0x1F00
247
248/*
249 * This macro will return the address of the access register for the
250 * queue  specified by qId
251 */
252#define IX_QMGR_Q_ACCESS_ADDR_GET(qId)\
253        (((qId) * (IX_QMGR_QUEACC_SIZE * IX_QMGR_NUM_BYTES_PER_WORD))\
254         + IX_QMGR_QUEACC0_OFFSET)
255
256/*
257 * Bit location of bit-3 of INT0SRCSELREG0 register to enabled
258 * sticky interrupt register.
259 */
260#define IX_QMGR_INT0SRCSELREG0_BIT3 3
261
262/*
263 * Variable declerations global to this file. Externs are followed by
264 * statics.
265 */
266extern UINT32 aqmBaseAddress;
267
268/*
269 * Function declarations.
270 */
271void
272ixQMgrAqmIfInit (void);
273
274void
275ixQMgrAqmIfUninit (void);
276
277unsigned
278ixQMgrAqmIfLog2 (unsigned number);
279
280void
281ixQMgrAqmIfQRegisterBitsWrite (IxQMgrQId qId, 
282                               UINT32 registerBaseAddrOffset,
283                               unsigned queuesPerRegWord,
284                               UINT32 value);
285
286void
287ixQMgrAqmIfQStatusCheckValsCalc (IxQMgrQId qId,
288                                 IxQMgrSourceId srcSel,
289                                 unsigned int *statusWordOffset,
290                                 UINT32 *checkValue,
291                                 UINT32 *mask);
292/*
293 * The Xscale software allways deals with logical addresses and so the
294 * base address of the AQM memory space is not a hardcoded value. This
295 * function must be called before any other function in this component.
296 * NO CHECKING is performed to ensure that the base address has been
297 * set.
298 */
299void
300ixQMgrAqmIfBaseAddressSet (UINT32 address);
301
302/*
303 * Get the base address of the AQM memory space.
304 */
305void
306ixQMgrAqmIfBaseAddressGet (UINT32 *address);
307
308/*
309 * Get the sram base address
310 */
311void
312ixQMgrAqmIfSramBaseAddressGet (UINT32 *address);
313
314/*
315 * Read a queue status
316 */
317void
318ixQMgrAqmIfQueStatRead (IxQMgrQId qId,
319                        IxQMgrQStatus* status);
320
321
322/*
323 *   Set INT0SRCSELREG0 Bit3
324 */ 
325void ixQMgrAqmIfIntSrcSelReg0Bit3Set (void);
326
327
328/*
329 * Set the interrupt source
330 */
331void
332ixQMgrAqmIfIntSrcSelWrite (IxQMgrQId qId,
333                           IxQMgrSourceId sourceId);
334
335/*
336 * Enable interruptson a queue
337 */
338void
339ixQMgrAqmIfQInterruptEnable (IxQMgrQId qId);
340
341/*
342 * Disable interrupt on a quee
343 */
344void
345ixQMgrAqmIfQInterruptDisable (IxQMgrQId qId);
346
347/*
348 * Write the config register of the specified queue
349 */
350void
351ixQMgrAqmIfQueCfgWrite (IxQMgrQId qId,
352                        IxQMgrQSizeInWords qSizeInWords,
353                        IxQMgrQEntrySizeInWords entrySizeInWords,
354                        UINT32 freeSRAMAddress);
355
356/*
357 * read fields from the config of the specified queue.
358 */
359void
360ixQMgrAqmIfQueCfgRead (IxQMgrQId qId,
361                       unsigned int numEntries,
362                       UINT32 *baseAddress,
363                       unsigned int *ne,
364                       unsigned int *nf,
365                       UINT32 *readPtr,
366                       UINT32 *writePtr);
367
368/*
369 * Set the ne and nf watermark level on a queue.
370 */
371void
372ixQMgrAqmIfWatermarkSet (IxQMgrQId qId,
373                         unsigned ne,
374                         unsigned nf);
375
376/* Inspect an entry without moving the read pointer */
377IX_STATUS
378ixQMgrAqmIfQPeek (IxQMgrQId qId,
379                  unsigned int entryIndex,
380                  unsigned int *entry);
381
382/* Modify an entry without moving the write pointer */
383IX_STATUS
384ixQMgrAqmIfQPoke (IxQMgrQId qId,
385                  unsigned int entryIndex,
386                  unsigned int *entry);
387
388/*
389 * Function prototype for inline functions. For description refers to
390 * the functions defintion below.
391 */
392IX_QMGR_AQMIF_INLINE void
393ixQMgrAqmIfWordWrite (VUINT32 *address,
394                      UINT32 word);
395
396IX_QMGR_AQMIF_INLINE void
397ixQMgrAqmIfWordRead (VUINT32 *address,
398                     UINT32 *word);
399
400IX_QMGR_AQMIF_INLINE void
401ixQMgrAqmIfQPop (IxQMgrQId qId,
402                 IxQMgrQEntrySizeInWords numWords,
403                 UINT32 *entry);
404
405IX_QMGR_AQMIF_INLINE void
406ixQMgrAqmIfQPush (IxQMgrQId qId,
407                  IxQMgrQEntrySizeInWords numWords,
408                  UINT32 *entry);
409
410IX_QMGR_AQMIF_INLINE void
411ixQMgrAqmIfQStatusRegsRead (IxQMgrDispatchGroup group, 
412                            UINT32 *qStatusWords);
413
414IX_QMGR_AQMIF_INLINE BOOL
415ixQMgrAqmIfQStatusCheck (UINT32 *oldQStatusWords,
416                         UINT32 *newQStatusWords,
417                         unsigned int statusWordOffset,                 
418                         UINT32 checkValue,
419                         UINT32 mask);
420
421IX_QMGR_AQMIF_INLINE BOOL
422ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId, 
423                             UINT32 registerBaseAddrOffset,
424                             unsigned queuesPerRegWord,
425                             unsigned relativeBitOffset,
426                             BOOL reset);
427
428IX_QMGR_AQMIF_INLINE BOOL
429ixQMgrAqmIfUnderflowCheck (IxQMgrQId qId);
430
431IX_QMGR_AQMIF_INLINE BOOL
432ixQMgrAqmIfOverflowCheck (IxQMgrQId qId);
433
434IX_QMGR_AQMIF_INLINE UINT32
435ixQMgrAqmIfQRegisterBitsRead (IxQMgrQId qId, 
436                              UINT32 registerBaseAddrOffset,
437                              unsigned queuesPerRegWord);
438IX_QMGR_AQMIF_INLINE void
439ixQMgrAqmIfQInterruptRegWrite (IxQMgrDispatchGroup group, 
440                               UINT32 reg);
441IX_QMGR_AQMIF_INLINE void
442ixQMgrAqmIfQInterruptRegRead (IxQMgrDispatchGroup group, 
443                              UINT32 *regVal);
444
445IX_QMGR_AQMIF_INLINE void
446ixQMgrAqmIfQueLowStatRead (IxQMgrQId qId,
447                           IxQMgrQStatus *status);
448
449IX_QMGR_AQMIF_INLINE void
450ixQMgrAqmIfQueUppStatRead (IxQMgrQId qId,
451                           IxQMgrQStatus *status);
452
453IX_QMGR_AQMIF_INLINE void
454ixQMgrAqmIfQueStatRead (IxQMgrQId qId, 
455                        IxQMgrQStatus *qStatus);
456
457IX_QMGR_AQMIF_INLINE unsigned
458ixQMgrAqmIfPow2NumDivide (unsigned numerator, 
459                          unsigned denominator);
460
461IX_QMGR_AQMIF_INLINE void
462ixQMgrAqmIfQInterruptEnableRegRead (IxQMgrDispatchGroup group, 
463                                    UINT32 *regVal);
464/*
465 * Inline functions
466 */
467
468/*
469 * This inline function is used by other QMgr components to write one
470 * word to the specified address.
471 */
472IX_QMGR_AQMIF_INLINE void
473ixQMgrAqmIfWordWrite (VUINT32 *address,
474                      UINT32 word)
475{
476    IX_OSAL_WRITE_LONG(address, word);
477}
478
479/*
480 * This inline function is used by other QMgr components to read a
481 * word from the specified address.
482 */
483IX_QMGR_AQMIF_INLINE void
484ixQMgrAqmIfWordRead (VUINT32 *address,
485                     UINT32 *word)
486{
487    *word = IX_OSAL_READ_LONG(address);
488}
489
490
491/*
492 * This inline function is used by other QMgr components to pop an
493 * entry off the specified queue.
494 */
495IX_QMGR_AQMIF_INLINE void
496ixQMgrAqmIfQPop (IxQMgrQId qId,
497                 IxQMgrQEntrySizeInWords numWords,
498                 UINT32 *entry)
499{
500    volatile UINT32 *accRegAddr;
501
502    accRegAddr = (UINT32*)(aqmBaseAddress +
503                           IX_QMGR_Q_ACCESS_ADDR_GET(qId));
504
505    switch (numWords)
506    {
507        case IX_QMGR_Q_ENTRY_SIZE1:
508            ixQMgrAqmIfWordRead (accRegAddr, entry);
509            break;
510        case IX_QMGR_Q_ENTRY_SIZE2:
511            ixQMgrAqmIfWordRead (accRegAddr++, entry++);
512            ixQMgrAqmIfWordRead (accRegAddr, entry);
513            break;
514        case IX_QMGR_Q_ENTRY_SIZE4:
515            ixQMgrAqmIfWordRead (accRegAddr++, entry++);
516            ixQMgrAqmIfWordRead (accRegAddr++, entry++);
517            ixQMgrAqmIfWordRead (accRegAddr++, entry++);
518            ixQMgrAqmIfWordRead (accRegAddr, entry);
519            break;
520        default:
521            IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfQPop");
522            break;
523    }
524}
525
526/*
527 * This inline function is used by other QMgr components to push an
528 * entry to the specified queue.
529 */
530IX_QMGR_AQMIF_INLINE void
531ixQMgrAqmIfQPush (IxQMgrQId qId,
532                  IxQMgrQEntrySizeInWords numWords,
533                  UINT32 *entry)
534{
535    volatile UINT32 *accRegAddr;
536
537    accRegAddr = (UINT32*)(aqmBaseAddress +
538                           IX_QMGR_Q_ACCESS_ADDR_GET(qId));
539   
540    switch (numWords)
541    {
542        case IX_QMGR_Q_ENTRY_SIZE1:
543            ixQMgrAqmIfWordWrite (accRegAddr, *entry);
544            break;
545        case IX_QMGR_Q_ENTRY_SIZE2:
546            ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
547            ixQMgrAqmIfWordWrite (accRegAddr, *entry);
548            break;
549        case IX_QMGR_Q_ENTRY_SIZE4:
550            ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
551            ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
552            ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
553            ixQMgrAqmIfWordWrite (accRegAddr, *entry);
554            break;
555        default:
556            IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfQPush");
557            break;
558    }
559}
560
561/*
562 * The AQM interrupt registers contains a bit for each AQM queue
563 * specifying the queue (s) that cause an interrupt to fire. This
564 * function is called by IxQMGrDispatcher component.
565 */
566IX_QMGR_AQMIF_INLINE void
567ixQMgrAqmIfQStatusRegsRead (IxQMgrDispatchGroup group, 
568                            UINT32 *qStatusWords)
569{
570    volatile UINT32 *regAddress = NULL;
571
572    if (group == IX_QMGR_QUELOW_GROUP)
573    {
574        regAddress = (UINT32*)(aqmBaseAddress +
575                               IX_QMGR_QUELOWSTAT0_OFFSET);
576
577        ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);
578        ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);
579        ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);
580        ixQMgrAqmIfWordRead (regAddress, qStatusWords);
581    }
582    else /* We have the upper queues */
583    {
584       /* Only need to read the Nearly Empty status register for
585        * queues 32-63 as for therse queues the interrtupt source
586        * condition is fixed to Nearly Empty
587        */
588        regAddress = (UINT32*)(aqmBaseAddress +
589                               IX_QMGR_QUEUPPSTAT0_OFFSET);
590        ixQMgrAqmIfWordRead (regAddress, qStatusWords);
591    }
592}
593
594
595/*
596 * This function check if the status for a queue has changed between
597 * 2 snapshots and if it has, that the status matches a particular
598 * value after masking.
599 */
600IX_QMGR_AQMIF_INLINE BOOL
601ixQMgrAqmIfQStatusCheck (UINT32 *oldQStatusWords,
602                         UINT32 *newQStatusWords,
603                         unsigned int statusWordOffset,                 
604                         UINT32 checkValue,
605                         UINT32 mask)
606{
607    if (((oldQStatusWords[statusWordOffset] & mask) != 
608         (newQStatusWords[statusWordOffset] & mask)) &&
609        ((newQStatusWords[statusWordOffset] & mask) == checkValue))
610    {
611        return TRUE;
612    }
613
614    return FALSE;
615}
616
617/*
618 * The AQM interrupt register contains a bit for each AQM queue
619 * specifying the queue (s) that cause an interrupt to fire. This
620 * function is called by IxQMgrDispatcher component.
621 */
622IX_QMGR_AQMIF_INLINE void
623ixQMgrAqmIfQInterruptRegRead (IxQMgrDispatchGroup group, 
624                              UINT32 *regVal)
625{
626    volatile UINT32 *regAddress;
627
628    if (group == IX_QMGR_QUELOW_GROUP)
629    {
630        regAddress = (UINT32*)(aqmBaseAddress +
631                               IX_QMGR_QINTREG0_OFFSET);
632    }
633    else
634    {
635        regAddress = (UINT32*)(aqmBaseAddress +
636                               IX_QMGR_QINTREG1_OFFSET);
637    }
638
639    ixQMgrAqmIfWordRead (regAddress, regVal);
640}
641
642/*
643 * The AQM interrupt enable register contains a bit for each AQM queue.
644 * This function reads the interrupt enable register. This
645 * function is called by IxQMgrDispatcher component.
646 */
647IX_QMGR_AQMIF_INLINE void
648ixQMgrAqmIfQInterruptEnableRegRead (IxQMgrDispatchGroup group, 
649                                    UINT32 *regVal)
650{
651    volatile UINT32 *regAddress;
652
653    if (group == IX_QMGR_QUELOW_GROUP)
654    {
655        regAddress = (UINT32*)(aqmBaseAddress +
656                               IX_QMGR_QUEIEREG0_OFFSET);
657    }
658    else
659    {
660        regAddress = (UINT32*)(aqmBaseAddress +
661                               IX_QMGR_QUEIEREG1_OFFSET);
662    }
663
664    ixQMgrAqmIfWordRead (regAddress, regVal);
665}
666
667
668/*
669 * This inline function will read the status bit of a queue
670 * specified by qId. If reset is TRUE the bit is cleared.
671 */
672IX_QMGR_AQMIF_INLINE BOOL
673ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId, 
674                             UINT32 registerBaseAddrOffset,
675                             unsigned queuesPerRegWord,
676                             unsigned relativeBitOffset,
677                             BOOL reset)
678{
679    UINT32 actualBitOffset;
680    volatile UINT32 *registerAddress;
681    UINT32 registerWord;
682
683    /*
684     * Calculate the registerAddress
685     * multiple queues split accross registers
686     */
687    registerAddress = (UINT32*)(aqmBaseAddress +
688                                registerBaseAddrOffset +
689                                ((qId / queuesPerRegWord) *
690                                 IX_QMGR_NUM_BYTES_PER_WORD));
691
692    /*
693     * Get the status word
694     */
695    ixQMgrAqmIfWordRead (registerAddress, &registerWord);
696   
697    /*
698     * Calculate the actualBitOffset
699     * status for multiple queues stored in one register
700     */
701    actualBitOffset = (relativeBitOffset + 1) <<
702        ((qId & (queuesPerRegWord - 1)) * (BITS_PER_WORD / queuesPerRegWord));
703
704    /* Check if the status bit is set */
705    if (registerWord & actualBitOffset)
706    {
707        /* Clear the bit if reset */
708        if (reset)
709        {
710            ixQMgrAqmIfWordWrite (registerAddress, registerWord & (~actualBitOffset));
711        }
712        return TRUE;
713    }
714
715    /* Bit not set */
716    return FALSE;
717}
718
719
720/*
721 * @ingroup IxQmgrAqmIfAPI
722 *
723 * @brief Read the underflow status of a queue
724 *
725 * This inline function will read the underflow status of a queue
726 * specified by qId.
727 *
728 */
729IX_QMGR_AQMIF_INLINE BOOL
730ixQMgrAqmIfUnderflowCheck (IxQMgrQId qId)
731{
732    if (qId < IX_QMGR_MIN_QUEUPP_QID)
733    {
734        return (ixQMgrAqmIfRegisterBitCheck (qId,
735                                             IX_QMGR_QUEUOSTAT0_OFFSET,
736                                             IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD,
737                                             IX_QMGR_UNDERFLOW_BIT_OFFSET,
738                                             TRUE/*reset*/));
739    }
740    else
741    {
742        /* Qs 32-63 have no underflow status */
743        return FALSE;
744    }
745}
746
747/*
748 * This inline function will read the overflow status of a queue
749 * specified by qId.
750 */
751IX_QMGR_AQMIF_INLINE BOOL
752ixQMgrAqmIfOverflowCheck (IxQMgrQId qId)
753{
754    if (qId < IX_QMGR_MIN_QUEUPP_QID)
755    {
756        return (ixQMgrAqmIfRegisterBitCheck (qId,
757                                             IX_QMGR_QUEUOSTAT0_OFFSET,
758                                             IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD,
759                                             IX_QMGR_OVERFLOW_BIT_OFFSET,
760                                             TRUE/*reset*/));
761    }
762    else
763    {
764        /* Qs 32-63 have no overflow status */
765        return FALSE;
766    }
767}
768
769/*
770 * This inline function will read the status bits of a queue
771 * specified by qId.
772 */
773IX_QMGR_AQMIF_INLINE UINT32
774ixQMgrAqmIfQRegisterBitsRead (IxQMgrQId qId, 
775                              UINT32 registerBaseAddrOffset,
776                              unsigned queuesPerRegWord)
777{
778    volatile UINT32 *registerAddress;
779    UINT32 registerWord;
780    UINT32 statusBitsMask;
781    UINT32 bitsPerQueue;
782
783    bitsPerQueue = BITS_PER_WORD / queuesPerRegWord;
784
785    /*
786     * Calculate the registerAddress
787     * multiple queues split accross registers
788     */
789    registerAddress = (UINT32*)(aqmBaseAddress +
790                                registerBaseAddrOffset +
791                                ((qId / queuesPerRegWord) *
792                                 IX_QMGR_NUM_BYTES_PER_WORD));
793    /*
794     * Read the status word
795     */
796    ixQMgrAqmIfWordRead (registerAddress, &registerWord);
797   
798
799    /*
800     * Calculate the mask for the status bits for this queue.
801     */
802    statusBitsMask = ((1 << bitsPerQueue) - 1);
803
804    /*
805     * Shift the status word so it is right justified
806     */   
807    registerWord >>= ((qId & (queuesPerRegWord - 1)) * bitsPerQueue);
808
809    /*
810     * Mask out all bar the status bits for this queue
811     */
812    return (registerWord &= statusBitsMask);
813}
814
815/*
816 * This function is called by IxQMgrDispatcher to set the contents of
817 * the AQM interrupt register.
818 */
819IX_QMGR_AQMIF_INLINE void
820ixQMgrAqmIfQInterruptRegWrite (IxQMgrDispatchGroup group, 
821                               UINT32 reg)
822{
823    volatile UINT32 *address;
824
825    if (group == IX_QMGR_QUELOW_GROUP)
826    {
827        address = (UINT32*)(aqmBaseAddress +
828                            IX_QMGR_QINTREG0_OFFSET);
829    }
830    else
831    {
832        address = (UINT32*)(aqmBaseAddress +
833                            IX_QMGR_QINTREG1_OFFSET);
834    }
835
836    ixQMgrAqmIfWordWrite (address, reg);
837}
838
839/*
840 * Read the status of a queue in the range 0-31.
841 *
842 * This function is used by other QMgr components to read the
843 * status of the queue specified by qId.
844 */
845IX_QMGR_AQMIF_INLINE void
846ixQMgrAqmIfQueLowStatRead (IxQMgrQId qId,
847                           IxQMgrQStatus *status)
848{
849    /* Read the general status bits */
850    *status = ixQMgrAqmIfQRegisterBitsRead (qId,
851                                            IX_QMGR_QUELOWSTAT0_OFFSET,
852                                            IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD);
853}
854
855/*
856 * This function will read the status of the queue specified
857 * by qId.
858 */
859IX_QMGR_AQMIF_INLINE void
860ixQMgrAqmIfQueUppStatRead (IxQMgrQId qId,
861                           IxQMgrQStatus *status)
862{
863    /* Reset the status bits */
864    *status = 0;
865
866    /*
867     * Check if the queue is nearly empty,
868     * N.b. QUPP stat register contains status for regs 32-63 at each
869     *      bit position so subtract 32 to get bit offset
870     */
871    if (ixQMgrAqmIfRegisterBitCheck ((qId - IX_QMGR_MIN_QUEUPP_QID),
872                                     IX_QMGR_QUEUPPSTAT0_OFFSET,
873                                     IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD,
874                                     0/*relativeBitOffset*/,
875                                     FALSE/*!reset*/))
876    {
877        *status |= IX_QMGR_Q_STATUS_NE_BIT_MASK;
878    }
879
880    /*
881     * Check if the queue is full,
882     * N.b. QUPP stat register contains status for regs 32-63 at each
883     *      bit position so subtract 32 to get bit offset
884     */
885    if (ixQMgrAqmIfRegisterBitCheck ((qId - IX_QMGR_MIN_QUEUPP_QID),
886                                     IX_QMGR_QUEUPPSTAT1_OFFSET,
887                                     IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD,
888                                     0/*relativeBitOffset*/,
889                                     FALSE/*!reset*/))
890    {
891        *status |= IX_QMGR_Q_STATUS_F_BIT_MASK;
892    }
893}
894
895/*
896 * This function is used by other QMgr components to read the
897 * status of the queue specified by qId.
898 */
899IX_QMGR_AQMIF_INLINE void
900ixQMgrAqmIfQueStatRead (IxQMgrQId qId, 
901                        IxQMgrQStatus *qStatus)
902{
903    if (qId < IX_QMGR_MIN_QUEUPP_QID)
904    {
905        ixQMgrAqmIfQueLowStatRead (qId, qStatus);
906    }
907    else
908    {
909        ixQMgrAqmIfQueUppStatRead (qId, qStatus);
910    }
911}
912
913
914/*
915 * This function performs a mod division
916 */
917IX_QMGR_AQMIF_INLINE unsigned
918ixQMgrAqmIfPow2NumDivide (unsigned numerator, 
919                          unsigned denominator)
920{
921    /* Number is evenly divisable by 2 */
922    return (numerator >> ixQMgrAqmIfLog2 (denominator));
923}
924
925/* Restore IX_COMPONENT_NAME */
926#undef IX_COMPONENT_NAME
927#define IX_COMPONENT_NAME IX_QMGR_AQMIF_SAVED_COMPONENT_NAME
928
929#endif/*IXQMGRAQMIF_P_H*/
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