1 | /** |
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2 | * @file IxQMgrAqmIf_p.h |
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3 | * |
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4 | * @author Intel Corporation |
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5 | * @date 30-Oct-2001 |
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6 | * |
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7 | * @brief The IxQMgrAqmIf sub-component provides a number of inline |
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8 | * functions for performing I/O on the AQM. |
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9 | * |
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10 | * Because some functions contained in this module are inline and are |
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11 | * used in other modules (within the QMgr component) the definitions are |
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12 | * contained in this header file. The "normal" use of inline functions |
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13 | * is to use the inline functions in the module in which they are |
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14 | * defined. In this case these inline functions are used in external |
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15 | * modules and therefore the use of "inline extern". What this means |
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16 | * is as follows: if a function foo is declared as "inline extern"this |
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17 | * definition is only used for inlining, in no case is the function |
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18 | * compiled on its own. If the compiler cannot inline the function it |
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19 | * becomes an external reference. Therefore in IxQMgrAqmIf.c all |
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20 | * inline functions are defined without the "inline extern" specifier |
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21 | * and so define the external references. In all other modules these |
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22 | * funtions are defined as "inline extern". |
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23 | * |
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24 | * |
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25 | * @par |
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26 | * IXP400 SW Release version 2.0 |
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27 | * |
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28 | * -- Intel Copyright Notice -- |
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29 | * |
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30 | * @par |
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31 | * Copyright 2002-2005 Intel Corporation All Rights Reserved. |
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32 | * |
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33 | * @par |
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34 | * The source code contained or described herein and all documents |
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35 | * related to the source code ("Material") are owned by Intel Corporation |
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36 | * or its suppliers or licensors. Title to the Material remains with |
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37 | * Intel Corporation or its suppliers and licensors. |
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38 | * |
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39 | * @par |
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40 | * The Material is protected by worldwide copyright and trade secret laws |
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41 | * and treaty provisions. No part of the Material may be used, copied, |
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42 | * reproduced, modified, published, uploaded, posted, transmitted, |
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43 | * distributed, or disclosed in any way except in accordance with the |
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44 | * applicable license agreement . |
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45 | * |
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46 | * @par |
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47 | * No license under any patent, copyright, trade secret or other |
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48 | * intellectual property right is granted to or conferred upon you by |
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49 | * disclosure or delivery of the Materials, either expressly, by |
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50 | * implication, inducement, estoppel, except in accordance with the |
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51 | * applicable license agreement. |
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52 | * |
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53 | * @par |
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54 | * Unless otherwise agreed by Intel in writing, you may not remove or |
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55 | * alter this notice or any other notice embedded in Materials by Intel |
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56 | * or Intel's suppliers or licensors in any way. |
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57 | * |
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58 | * @par |
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59 | * For further details, please see the file README.TXT distributed with |
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60 | * this software. |
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61 | * |
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62 | * @par |
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63 | * -- End Intel Copyright Notice -- |
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64 | */ |
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65 | |
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66 | #ifndef IXQMGRAQMIF_P_H |
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67 | #define IXQMGRAQMIF_P_H |
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68 | |
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69 | #include "IxOsalTypes.h" |
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70 | |
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71 | /* |
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72 | * inline definition |
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73 | */ |
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74 | |
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75 | #ifdef IX_OSAL_INLINE_ALL |
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76 | /* If IX_OSAL_INLINE_ALL is set then each inlineable API functions will be defined as |
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77 | inline functions */ |
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78 | #define IX_QMGR_AQMIF_INLINE IX_OSAL_INLINE_EXTERN |
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79 | #else |
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80 | #ifdef IXQMGRAQMIF_C |
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81 | #ifndef IX_QMGR_AQMIF_INLINE |
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82 | #define IX_QMGR_AQMIF_INLINE |
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83 | #endif |
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84 | #else |
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85 | #ifndef IX_QMGR_AQMIF_INLINE |
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86 | #define IX_QMGR_AQMIF_INLINE IX_OSAL_INLINE_EXTERN |
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87 | #endif |
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88 | #endif /* IXQMGRAQMIF_C */ |
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89 | #endif /* IX_OSAL_INLINE */ |
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90 | |
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91 | |
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92 | /* |
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93 | * User defined include files. |
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94 | */ |
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95 | #include "IxQMgr.h" |
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96 | #include "IxQMgrLog_p.h" |
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97 | #include "IxQMgrQCfg_p.h" |
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98 | |
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99 | /* Because this file contains inline functions which will be compiled into |
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100 | * other components, we need to ensure that the IX_COMPONENT_NAME define |
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101 | * is set to ix_qmgr while this code is being compiled. This will ensure |
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102 | * that the correct implementation is provided for the memory access macros |
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103 | * IX_OSAL_READ_LONG and IX_OSAL_WRITE_LONG which are used in this file. |
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104 | * This must be done before including "IxOsalMemAccess.h" |
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105 | */ |
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106 | #define IX_QMGR_AQMIF_SAVED_COMPONENT_NAME IX_COMPONENT_NAME |
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107 | #undef IX_COMPONENT_NAME |
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108 | #define IX_COMPONENT_NAME ix_qmgr |
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109 | #include "IxOsal.h" |
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110 | |
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111 | /* |
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112 | * #defines and macros used in this file. |
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113 | */ |
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114 | |
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115 | /* Number of bytes per word */ |
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116 | #define IX_QMGR_NUM_BYTES_PER_WORD 4 |
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117 | |
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118 | /* Underflow bit mask */ |
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119 | #define IX_QMGR_UNDERFLOW_BIT_OFFSET 0x0 |
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120 | |
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121 | /* Overflow bit mask */ |
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122 | #define IX_QMGR_OVERFLOW_BIT_OFFSET 0x1 |
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123 | |
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124 | /* Queue access register, queue 0 */ |
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125 | #define IX_QMGR_QUEACC0_OFFSET 0x0000 |
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126 | |
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127 | /* Size of queue access register in words */ |
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128 | #define IX_QMGR_QUEACC_SIZE 0x4/*words*/ |
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129 | |
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130 | /* Queue status register, queues 0-7 */ |
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131 | #define IX_QMGR_QUELOWSTAT0_OFFSET (IX_QMGR_QUEACC0_OFFSET +\ |
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132 | (IX_QMGR_MAX_NUM_QUEUES * IX_QMGR_QUEACC_SIZE * IX_QMGR_NUM_BYTES_PER_WORD)) |
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133 | |
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134 | /* Queue status register, queues 8-15 */ |
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135 | #define IX_QMGR_QUELOWSTAT1_OFFSET (IX_QMGR_QUELOWSTAT0_OFFSET +\ |
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136 | IX_QMGR_NUM_BYTES_PER_WORD) |
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137 | |
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138 | /* Queue status register, queues 16-23 */ |
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139 | #define IX_QMGR_QUELOWSTAT2_OFFSET (IX_QMGR_QUELOWSTAT1_OFFSET +\ |
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140 | IX_QMGR_NUM_BYTES_PER_WORD) |
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141 | |
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142 | /* Queue status register, queues 24-31 */ |
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143 | #define IX_QMGR_QUELOWSTAT3_OFFSET (IX_QMGR_QUELOWSTAT2_OFFSET +\ |
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144 | IX_QMGR_NUM_BYTES_PER_WORD) |
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145 | |
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146 | /* Queue status register Q status bits mask */ |
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147 | #define IX_QMGR_QUELOWSTAT_QUE_STS_BITS_MASK 0xF |
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148 | |
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149 | /* Size of queue 0-31 status register */ |
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150 | #define IX_QMGR_QUELOWSTAT_SIZE 0x4 /*words*/ |
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151 | |
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152 | /* The number of queues' status specified per word */ |
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153 | #define IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD 0x8 |
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154 | |
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155 | /* Queue UF/OF status register queues 0-15 */ |
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156 | #define IX_QMGR_QUEUOSTAT0_OFFSET (IX_QMGR_QUELOWSTAT3_OFFSET +\ |
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157 | IX_QMGR_NUM_BYTES_PER_WORD) |
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158 | /* Queue UF/OF status register queues 16-31 */ |
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159 | #define IX_QMGR_QUEUOSTAT1_OFFSET (IX_QMGR_QUEUOSTAT0_OFFSET +\ |
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160 | IX_QMGR_NUM_BYTES_PER_WORD) |
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161 | |
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162 | /* The number of queues' underflow/overflow status specified per word */ |
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163 | #define IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD 0x10 |
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164 | |
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165 | /* Queue NE status register, queues 32-63 */ |
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166 | #define IX_QMGR_QUEUPPSTAT0_OFFSET (IX_QMGR_QUEUOSTAT1_OFFSET +\ |
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167 | IX_QMGR_NUM_BYTES_PER_WORD) |
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168 | |
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169 | /* Queue F status register, queues 32-63 */ |
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170 | #define IX_QMGR_QUEUPPSTAT1_OFFSET (IX_QMGR_QUEUPPSTAT0_OFFSET +\ |
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171 | IX_QMGR_NUM_BYTES_PER_WORD) |
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172 | |
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173 | /* Size of queue 32-63 status register */ |
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174 | #define IX_QMGR_QUEUPPSTAT_SIZE 0x2 /*words*/ |
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175 | |
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176 | /* The number of queues' status specified per word */ |
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177 | #define IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD 0x20 |
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178 | |
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179 | /* Queue INT source select register, queues 0-7 */ |
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180 | #define IX_QMGR_INT0SRCSELREG0_OFFSET (IX_QMGR_QUEUPPSTAT1_OFFSET +\ |
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181 | IX_QMGR_NUM_BYTES_PER_WORD) |
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182 | |
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183 | /* Queue INT source select register, queues 8-15 */ |
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184 | #define IX_QMGR_INT0SRCSELREG1_OFFSET (IX_QMGR_INT0SRCSELREG0_OFFSET+\ |
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185 | IX_QMGR_NUM_BYTES_PER_WORD) |
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186 | |
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187 | /* Queue INT source select register, queues 16-23 */ |
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188 | #define IX_QMGR_INT0SRCSELREG2_OFFSET (IX_QMGR_INT0SRCSELREG1_OFFSET+\ |
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189 | IX_QMGR_NUM_BYTES_PER_WORD) |
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190 | |
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191 | /* Queue INT source select register, queues 24-31 */ |
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192 | #define IX_QMGR_INT0SRCSELREG3_OFFSET (IX_QMGR_INT0SRCSELREG2_OFFSET+\ |
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193 | IX_QMGR_NUM_BYTES_PER_WORD) |
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194 | |
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195 | /* Size of interrupt source select reegister */ |
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196 | #define IX_QMGR_INT0SRCSELREG_SIZE 0x4 /*words*/ |
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197 | |
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198 | /* The number of queues' interrupt source select specified per word*/ |
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199 | #define IX_QMGR_INTSRC_NUM_QUE_PER_WORD 0x8 |
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200 | |
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201 | /* Queue INT enable register, queues 0-31 */ |
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202 | #define IX_QMGR_QUEIEREG0_OFFSET (IX_QMGR_INT0SRCSELREG3_OFFSET +\ |
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203 | IX_QMGR_NUM_BYTES_PER_WORD) |
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204 | |
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205 | /* Queue INT enable register, queues 32-63 */ |
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206 | #define IX_QMGR_QUEIEREG1_OFFSET (IX_QMGR_QUEIEREG0_OFFSET +\ |
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207 | IX_QMGR_NUM_BYTES_PER_WORD) |
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208 | |
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209 | /* Queue INT register, queues 0-31 */ |
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210 | #define IX_QMGR_QINTREG0_OFFSET (IX_QMGR_QUEIEREG1_OFFSET +\ |
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211 | IX_QMGR_NUM_BYTES_PER_WORD) |
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212 | |
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213 | /* Queue INT register, queues 32-63 */ |
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214 | #define IX_QMGR_QINTREG1_OFFSET (IX_QMGR_QINTREG0_OFFSET +\ |
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215 | IX_QMGR_NUM_BYTES_PER_WORD) |
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216 | |
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217 | /* Size of interrupt register */ |
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218 | #define IX_QMGR_QINTREG_SIZE 0x2 /*words*/ |
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219 | |
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220 | /* Number of queues' status specified per word */ |
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221 | #define IX_QMGR_QINTREG_NUM_QUE_PER_WORD 0x20 |
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222 | |
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223 | /* Number of bits per queue interrupt status */ |
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224 | #define IX_QMGR_QINTREG_BITS_PER_QUEUE 0x1 |
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225 | #define IX_QMGR_QINTREG_BIT_OFFSET 0x1 |
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226 | |
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227 | /* Size of address space not used by AQM */ |
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228 | #define IX_QMGR_AQM_UNUSED_ADDRESS_SPACE_SIZE_IN_BYTES 0x1bC0 |
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229 | |
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230 | /* Queue config register, queue 0 */ |
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231 | #define IX_QMGR_QUECONFIG_BASE_OFFSET (IX_QMGR_QINTREG1_OFFSET +\ |
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232 | IX_QMGR_NUM_BYTES_PER_WORD +\ |
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233 | IX_QMGR_AQM_UNUSED_ADDRESS_SPACE_SIZE_IN_BYTES) |
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234 | |
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235 | /* Total size of configuration words */ |
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236 | #define IX_QMGR_QUECONFIG_SIZE 0x100 |
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237 | |
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238 | /* Start of SRAM queue buffer space */ |
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239 | #define IX_QMGR_QUEBUFFER_SPACE_OFFSET (IX_QMGR_QUECONFIG_BASE_OFFSET +\ |
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240 | IX_QMGR_MAX_NUM_QUEUES * IX_QMGR_NUM_BYTES_PER_WORD) |
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241 | |
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242 | /* Total bits in a word */ |
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243 | #define BITS_PER_WORD 32 |
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244 | |
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245 | /* Size of queue buffer space */ |
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246 | #define IX_QMGR_QUE_BUFFER_SPACE_SIZE 0x1F00 |
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247 | |
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248 | /* |
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249 | * This macro will return the address of the access register for the |
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250 | * queue specified by qId |
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251 | */ |
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252 | #define IX_QMGR_Q_ACCESS_ADDR_GET(qId)\ |
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253 | (((qId) * (IX_QMGR_QUEACC_SIZE * IX_QMGR_NUM_BYTES_PER_WORD))\ |
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254 | + IX_QMGR_QUEACC0_OFFSET) |
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255 | |
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256 | /* |
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257 | * Bit location of bit-3 of INT0SRCSELREG0 register to enabled |
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258 | * sticky interrupt register. |
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259 | */ |
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260 | #define IX_QMGR_INT0SRCSELREG0_BIT3 3 |
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261 | |
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262 | /* |
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263 | * Variable declerations global to this file. Externs are followed by |
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264 | * statics. |
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265 | */ |
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266 | extern UINT32 aqmBaseAddress; |
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267 | |
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268 | /* |
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269 | * Function declarations. |
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270 | */ |
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271 | void |
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272 | ixQMgrAqmIfInit (void); |
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273 | |
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274 | void |
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275 | ixQMgrAqmIfUninit (void); |
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276 | |
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277 | unsigned |
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278 | ixQMgrAqmIfLog2 (unsigned number); |
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279 | |
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280 | void |
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281 | ixQMgrAqmIfQRegisterBitsWrite (IxQMgrQId qId, |
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282 | UINT32 registerBaseAddrOffset, |
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283 | unsigned queuesPerRegWord, |
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284 | UINT32 value); |
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285 | |
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286 | void |
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287 | ixQMgrAqmIfQStatusCheckValsCalc (IxQMgrQId qId, |
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288 | IxQMgrSourceId srcSel, |
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289 | unsigned int *statusWordOffset, |
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290 | UINT32 *checkValue, |
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291 | UINT32 *mask); |
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292 | /* |
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293 | * The Xscale software allways deals with logical addresses and so the |
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294 | * base address of the AQM memory space is not a hardcoded value. This |
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295 | * function must be called before any other function in this component. |
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296 | * NO CHECKING is performed to ensure that the base address has been |
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297 | * set. |
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298 | */ |
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299 | void |
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300 | ixQMgrAqmIfBaseAddressSet (UINT32 address); |
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301 | |
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302 | /* |
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303 | * Get the base address of the AQM memory space. |
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304 | */ |
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305 | void |
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306 | ixQMgrAqmIfBaseAddressGet (UINT32 *address); |
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307 | |
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308 | /* |
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309 | * Get the sram base address |
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310 | */ |
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311 | void |
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312 | ixQMgrAqmIfSramBaseAddressGet (UINT32 *address); |
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313 | |
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314 | /* |
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315 | * Read a queue status |
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316 | */ |
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317 | void |
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318 | ixQMgrAqmIfQueStatRead (IxQMgrQId qId, |
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319 | IxQMgrQStatus* status); |
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320 | |
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321 | |
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322 | /* |
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323 | * Set INT0SRCSELREG0 Bit3 |
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324 | */ |
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325 | void ixQMgrAqmIfIntSrcSelReg0Bit3Set (void); |
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326 | |
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327 | |
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328 | /* |
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329 | * Set the interrupt source |
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330 | */ |
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331 | void |
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332 | ixQMgrAqmIfIntSrcSelWrite (IxQMgrQId qId, |
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333 | IxQMgrSourceId sourceId); |
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334 | |
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335 | /* |
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336 | * Enable interruptson a queue |
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337 | */ |
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338 | void |
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339 | ixQMgrAqmIfQInterruptEnable (IxQMgrQId qId); |
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340 | |
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341 | /* |
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342 | * Disable interrupt on a quee |
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343 | */ |
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344 | void |
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345 | ixQMgrAqmIfQInterruptDisable (IxQMgrQId qId); |
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346 | |
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347 | /* |
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348 | * Write the config register of the specified queue |
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349 | */ |
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350 | void |
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351 | ixQMgrAqmIfQueCfgWrite (IxQMgrQId qId, |
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352 | IxQMgrQSizeInWords qSizeInWords, |
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353 | IxQMgrQEntrySizeInWords entrySizeInWords, |
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354 | UINT32 freeSRAMAddress); |
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355 | |
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356 | /* |
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357 | * read fields from the config of the specified queue. |
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358 | */ |
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359 | void |
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360 | ixQMgrAqmIfQueCfgRead (IxQMgrQId qId, |
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361 | unsigned int numEntries, |
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362 | UINT32 *baseAddress, |
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363 | unsigned int *ne, |
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364 | unsigned int *nf, |
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365 | UINT32 *readPtr, |
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366 | UINT32 *writePtr); |
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367 | |
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368 | /* |
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369 | * Set the ne and nf watermark level on a queue. |
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370 | */ |
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371 | void |
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372 | ixQMgrAqmIfWatermarkSet (IxQMgrQId qId, |
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373 | unsigned ne, |
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374 | unsigned nf); |
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375 | |
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376 | /* Inspect an entry without moving the read pointer */ |
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377 | IX_STATUS |
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378 | ixQMgrAqmIfQPeek (IxQMgrQId qId, |
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379 | unsigned int entryIndex, |
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380 | unsigned int *entry); |
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381 | |
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382 | /* Modify an entry without moving the write pointer */ |
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383 | IX_STATUS |
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384 | ixQMgrAqmIfQPoke (IxQMgrQId qId, |
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385 | unsigned int entryIndex, |
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386 | unsigned int *entry); |
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387 | |
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388 | /* |
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389 | * Function prototype for inline functions. For description refers to |
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390 | * the functions defintion below. |
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391 | */ |
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392 | IX_QMGR_AQMIF_INLINE void |
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393 | ixQMgrAqmIfWordWrite (VUINT32 *address, |
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394 | UINT32 word); |
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395 | |
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396 | IX_QMGR_AQMIF_INLINE void |
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397 | ixQMgrAqmIfWordRead (VUINT32 *address, |
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398 | UINT32 *word); |
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399 | |
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400 | IX_QMGR_AQMIF_INLINE void |
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401 | ixQMgrAqmIfQPop (IxQMgrQId qId, |
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402 | IxQMgrQEntrySizeInWords numWords, |
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403 | UINT32 *entry); |
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404 | |
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405 | IX_QMGR_AQMIF_INLINE void |
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406 | ixQMgrAqmIfQPush (IxQMgrQId qId, |
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407 | IxQMgrQEntrySizeInWords numWords, |
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408 | UINT32 *entry); |
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409 | |
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410 | IX_QMGR_AQMIF_INLINE void |
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411 | ixQMgrAqmIfQStatusRegsRead (IxQMgrDispatchGroup group, |
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412 | UINT32 *qStatusWords); |
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413 | |
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414 | IX_QMGR_AQMIF_INLINE BOOL |
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415 | ixQMgrAqmIfQStatusCheck (UINT32 *oldQStatusWords, |
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416 | UINT32 *newQStatusWords, |
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417 | unsigned int statusWordOffset, |
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418 | UINT32 checkValue, |
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419 | UINT32 mask); |
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420 | |
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421 | IX_QMGR_AQMIF_INLINE BOOL |
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422 | ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId, |
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423 | UINT32 registerBaseAddrOffset, |
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424 | unsigned queuesPerRegWord, |
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425 | unsigned relativeBitOffset, |
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426 | BOOL reset); |
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427 | |
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428 | IX_QMGR_AQMIF_INLINE BOOL |
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429 | ixQMgrAqmIfUnderflowCheck (IxQMgrQId qId); |
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430 | |
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431 | IX_QMGR_AQMIF_INLINE BOOL |
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432 | ixQMgrAqmIfOverflowCheck (IxQMgrQId qId); |
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433 | |
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434 | IX_QMGR_AQMIF_INLINE UINT32 |
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435 | ixQMgrAqmIfQRegisterBitsRead (IxQMgrQId qId, |
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436 | UINT32 registerBaseAddrOffset, |
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437 | unsigned queuesPerRegWord); |
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438 | IX_QMGR_AQMIF_INLINE void |
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439 | ixQMgrAqmIfQInterruptRegWrite (IxQMgrDispatchGroup group, |
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440 | UINT32 reg); |
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441 | IX_QMGR_AQMIF_INLINE void |
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442 | ixQMgrAqmIfQInterruptRegRead (IxQMgrDispatchGroup group, |
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443 | UINT32 *regVal); |
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444 | |
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445 | IX_QMGR_AQMIF_INLINE void |
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446 | ixQMgrAqmIfQueLowStatRead (IxQMgrQId qId, |
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447 | IxQMgrQStatus *status); |
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448 | |
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449 | IX_QMGR_AQMIF_INLINE void |
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450 | ixQMgrAqmIfQueUppStatRead (IxQMgrQId qId, |
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451 | IxQMgrQStatus *status); |
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452 | |
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453 | IX_QMGR_AQMIF_INLINE void |
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454 | ixQMgrAqmIfQueStatRead (IxQMgrQId qId, |
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455 | IxQMgrQStatus *qStatus); |
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456 | |
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457 | IX_QMGR_AQMIF_INLINE unsigned |
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458 | ixQMgrAqmIfPow2NumDivide (unsigned numerator, |
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459 | unsigned denominator); |
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460 | |
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461 | IX_QMGR_AQMIF_INLINE void |
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462 | ixQMgrAqmIfQInterruptEnableRegRead (IxQMgrDispatchGroup group, |
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463 | UINT32 *regVal); |
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464 | /* |
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465 | * Inline functions |
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466 | */ |
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467 | |
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468 | /* |
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469 | * This inline function is used by other QMgr components to write one |
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470 | * word to the specified address. |
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471 | */ |
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472 | IX_QMGR_AQMIF_INLINE void |
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473 | ixQMgrAqmIfWordWrite (VUINT32 *address, |
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474 | UINT32 word) |
---|
475 | { |
---|
476 | IX_OSAL_WRITE_LONG(address, word); |
---|
477 | } |
---|
478 | |
---|
479 | /* |
---|
480 | * This inline function is used by other QMgr components to read a |
---|
481 | * word from the specified address. |
---|
482 | */ |
---|
483 | IX_QMGR_AQMIF_INLINE void |
---|
484 | ixQMgrAqmIfWordRead (VUINT32 *address, |
---|
485 | UINT32 *word) |
---|
486 | { |
---|
487 | *word = IX_OSAL_READ_LONG(address); |
---|
488 | } |
---|
489 | |
---|
490 | |
---|
491 | /* |
---|
492 | * This inline function is used by other QMgr components to pop an |
---|
493 | * entry off the specified queue. |
---|
494 | */ |
---|
495 | IX_QMGR_AQMIF_INLINE void |
---|
496 | ixQMgrAqmIfQPop (IxQMgrQId qId, |
---|
497 | IxQMgrQEntrySizeInWords numWords, |
---|
498 | UINT32 *entry) |
---|
499 | { |
---|
500 | volatile UINT32 *accRegAddr; |
---|
501 | |
---|
502 | accRegAddr = (UINT32*)(aqmBaseAddress + |
---|
503 | IX_QMGR_Q_ACCESS_ADDR_GET(qId)); |
---|
504 | |
---|
505 | switch (numWords) |
---|
506 | { |
---|
507 | case IX_QMGR_Q_ENTRY_SIZE1: |
---|
508 | ixQMgrAqmIfWordRead (accRegAddr, entry); |
---|
509 | break; |
---|
510 | case IX_QMGR_Q_ENTRY_SIZE2: |
---|
511 | ixQMgrAqmIfWordRead (accRegAddr++, entry++); |
---|
512 | ixQMgrAqmIfWordRead (accRegAddr, entry); |
---|
513 | break; |
---|
514 | case IX_QMGR_Q_ENTRY_SIZE4: |
---|
515 | ixQMgrAqmIfWordRead (accRegAddr++, entry++); |
---|
516 | ixQMgrAqmIfWordRead (accRegAddr++, entry++); |
---|
517 | ixQMgrAqmIfWordRead (accRegAddr++, entry++); |
---|
518 | ixQMgrAqmIfWordRead (accRegAddr, entry); |
---|
519 | break; |
---|
520 | default: |
---|
521 | IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfQPop"); |
---|
522 | break; |
---|
523 | } |
---|
524 | } |
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525 | |
---|
526 | /* |
---|
527 | * This inline function is used by other QMgr components to push an |
---|
528 | * entry to the specified queue. |
---|
529 | */ |
---|
530 | IX_QMGR_AQMIF_INLINE void |
---|
531 | ixQMgrAqmIfQPush (IxQMgrQId qId, |
---|
532 | IxQMgrQEntrySizeInWords numWords, |
---|
533 | UINT32 *entry) |
---|
534 | { |
---|
535 | volatile UINT32 *accRegAddr; |
---|
536 | |
---|
537 | accRegAddr = (UINT32*)(aqmBaseAddress + |
---|
538 | IX_QMGR_Q_ACCESS_ADDR_GET(qId)); |
---|
539 | |
---|
540 | switch (numWords) |
---|
541 | { |
---|
542 | case IX_QMGR_Q_ENTRY_SIZE1: |
---|
543 | ixQMgrAqmIfWordWrite (accRegAddr, *entry); |
---|
544 | break; |
---|
545 | case IX_QMGR_Q_ENTRY_SIZE2: |
---|
546 | ixQMgrAqmIfWordWrite (accRegAddr++, *entry++); |
---|
547 | ixQMgrAqmIfWordWrite (accRegAddr, *entry); |
---|
548 | break; |
---|
549 | case IX_QMGR_Q_ENTRY_SIZE4: |
---|
550 | ixQMgrAqmIfWordWrite (accRegAddr++, *entry++); |
---|
551 | ixQMgrAqmIfWordWrite (accRegAddr++, *entry++); |
---|
552 | ixQMgrAqmIfWordWrite (accRegAddr++, *entry++); |
---|
553 | ixQMgrAqmIfWordWrite (accRegAddr, *entry); |
---|
554 | break; |
---|
555 | default: |
---|
556 | IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfQPush"); |
---|
557 | break; |
---|
558 | } |
---|
559 | } |
---|
560 | |
---|
561 | /* |
---|
562 | * The AQM interrupt registers contains a bit for each AQM queue |
---|
563 | * specifying the queue (s) that cause an interrupt to fire. This |
---|
564 | * function is called by IxQMGrDispatcher component. |
---|
565 | */ |
---|
566 | IX_QMGR_AQMIF_INLINE void |
---|
567 | ixQMgrAqmIfQStatusRegsRead (IxQMgrDispatchGroup group, |
---|
568 | UINT32 *qStatusWords) |
---|
569 | { |
---|
570 | volatile UINT32 *regAddress = NULL; |
---|
571 | |
---|
572 | if (group == IX_QMGR_QUELOW_GROUP) |
---|
573 | { |
---|
574 | regAddress = (UINT32*)(aqmBaseAddress + |
---|
575 | IX_QMGR_QUELOWSTAT0_OFFSET); |
---|
576 | |
---|
577 | ixQMgrAqmIfWordRead (regAddress++, qStatusWords++); |
---|
578 | ixQMgrAqmIfWordRead (regAddress++, qStatusWords++); |
---|
579 | ixQMgrAqmIfWordRead (regAddress++, qStatusWords++); |
---|
580 | ixQMgrAqmIfWordRead (regAddress, qStatusWords); |
---|
581 | } |
---|
582 | else /* We have the upper queues */ |
---|
583 | { |
---|
584 | /* Only need to read the Nearly Empty status register for |
---|
585 | * queues 32-63 as for therse queues the interrtupt source |
---|
586 | * condition is fixed to Nearly Empty |
---|
587 | */ |
---|
588 | regAddress = (UINT32*)(aqmBaseAddress + |
---|
589 | IX_QMGR_QUEUPPSTAT0_OFFSET); |
---|
590 | ixQMgrAqmIfWordRead (regAddress, qStatusWords); |
---|
591 | } |
---|
592 | } |
---|
593 | |
---|
594 | |
---|
595 | /* |
---|
596 | * This function check if the status for a queue has changed between |
---|
597 | * 2 snapshots and if it has, that the status matches a particular |
---|
598 | * value after masking. |
---|
599 | */ |
---|
600 | IX_QMGR_AQMIF_INLINE BOOL |
---|
601 | ixQMgrAqmIfQStatusCheck (UINT32 *oldQStatusWords, |
---|
602 | UINT32 *newQStatusWords, |
---|
603 | unsigned int statusWordOffset, |
---|
604 | UINT32 checkValue, |
---|
605 | UINT32 mask) |
---|
606 | { |
---|
607 | if (((oldQStatusWords[statusWordOffset] & mask) != |
---|
608 | (newQStatusWords[statusWordOffset] & mask)) && |
---|
609 | ((newQStatusWords[statusWordOffset] & mask) == checkValue)) |
---|
610 | { |
---|
611 | return TRUE; |
---|
612 | } |
---|
613 | |
---|
614 | return FALSE; |
---|
615 | } |
---|
616 | |
---|
617 | /* |
---|
618 | * The AQM interrupt register contains a bit for each AQM queue |
---|
619 | * specifying the queue (s) that cause an interrupt to fire. This |
---|
620 | * function is called by IxQMgrDispatcher component. |
---|
621 | */ |
---|
622 | IX_QMGR_AQMIF_INLINE void |
---|
623 | ixQMgrAqmIfQInterruptRegRead (IxQMgrDispatchGroup group, |
---|
624 | UINT32 *regVal) |
---|
625 | { |
---|
626 | volatile UINT32 *regAddress; |
---|
627 | |
---|
628 | if (group == IX_QMGR_QUELOW_GROUP) |
---|
629 | { |
---|
630 | regAddress = (UINT32*)(aqmBaseAddress + |
---|
631 | IX_QMGR_QINTREG0_OFFSET); |
---|
632 | } |
---|
633 | else |
---|
634 | { |
---|
635 | regAddress = (UINT32*)(aqmBaseAddress + |
---|
636 | IX_QMGR_QINTREG1_OFFSET); |
---|
637 | } |
---|
638 | |
---|
639 | ixQMgrAqmIfWordRead (regAddress, regVal); |
---|
640 | } |
---|
641 | |
---|
642 | /* |
---|
643 | * The AQM interrupt enable register contains a bit for each AQM queue. |
---|
644 | * This function reads the interrupt enable register. This |
---|
645 | * function is called by IxQMgrDispatcher component. |
---|
646 | */ |
---|
647 | IX_QMGR_AQMIF_INLINE void |
---|
648 | ixQMgrAqmIfQInterruptEnableRegRead (IxQMgrDispatchGroup group, |
---|
649 | UINT32 *regVal) |
---|
650 | { |
---|
651 | volatile UINT32 *regAddress; |
---|
652 | |
---|
653 | if (group == IX_QMGR_QUELOW_GROUP) |
---|
654 | { |
---|
655 | regAddress = (UINT32*)(aqmBaseAddress + |
---|
656 | IX_QMGR_QUEIEREG0_OFFSET); |
---|
657 | } |
---|
658 | else |
---|
659 | { |
---|
660 | regAddress = (UINT32*)(aqmBaseAddress + |
---|
661 | IX_QMGR_QUEIEREG1_OFFSET); |
---|
662 | } |
---|
663 | |
---|
664 | ixQMgrAqmIfWordRead (regAddress, regVal); |
---|
665 | } |
---|
666 | |
---|
667 | |
---|
668 | /* |
---|
669 | * This inline function will read the status bit of a queue |
---|
670 | * specified by qId. If reset is TRUE the bit is cleared. |
---|
671 | */ |
---|
672 | IX_QMGR_AQMIF_INLINE BOOL |
---|
673 | ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId, |
---|
674 | UINT32 registerBaseAddrOffset, |
---|
675 | unsigned queuesPerRegWord, |
---|
676 | unsigned relativeBitOffset, |
---|
677 | BOOL reset) |
---|
678 | { |
---|
679 | UINT32 actualBitOffset; |
---|
680 | volatile UINT32 *registerAddress; |
---|
681 | UINT32 registerWord; |
---|
682 | |
---|
683 | /* |
---|
684 | * Calculate the registerAddress |
---|
685 | * multiple queues split accross registers |
---|
686 | */ |
---|
687 | registerAddress = (UINT32*)(aqmBaseAddress + |
---|
688 | registerBaseAddrOffset + |
---|
689 | ((qId / queuesPerRegWord) * |
---|
690 | IX_QMGR_NUM_BYTES_PER_WORD)); |
---|
691 | |
---|
692 | /* |
---|
693 | * Get the status word |
---|
694 | */ |
---|
695 | ixQMgrAqmIfWordRead (registerAddress, ®isterWord); |
---|
696 | |
---|
697 | /* |
---|
698 | * Calculate the actualBitOffset |
---|
699 | * status for multiple queues stored in one register |
---|
700 | */ |
---|
701 | actualBitOffset = (relativeBitOffset + 1) << |
---|
702 | ((qId & (queuesPerRegWord - 1)) * (BITS_PER_WORD / queuesPerRegWord)); |
---|
703 | |
---|
704 | /* Check if the status bit is set */ |
---|
705 | if (registerWord & actualBitOffset) |
---|
706 | { |
---|
707 | /* Clear the bit if reset */ |
---|
708 | if (reset) |
---|
709 | { |
---|
710 | ixQMgrAqmIfWordWrite (registerAddress, registerWord & (~actualBitOffset)); |
---|
711 | } |
---|
712 | return TRUE; |
---|
713 | } |
---|
714 | |
---|
715 | /* Bit not set */ |
---|
716 | return FALSE; |
---|
717 | } |
---|
718 | |
---|
719 | |
---|
720 | /* |
---|
721 | * @ingroup IxQmgrAqmIfAPI |
---|
722 | * |
---|
723 | * @brief Read the underflow status of a queue |
---|
724 | * |
---|
725 | * This inline function will read the underflow status of a queue |
---|
726 | * specified by qId. |
---|
727 | * |
---|
728 | */ |
---|
729 | IX_QMGR_AQMIF_INLINE BOOL |
---|
730 | ixQMgrAqmIfUnderflowCheck (IxQMgrQId qId) |
---|
731 | { |
---|
732 | if (qId < IX_QMGR_MIN_QUEUPP_QID) |
---|
733 | { |
---|
734 | return (ixQMgrAqmIfRegisterBitCheck (qId, |
---|
735 | IX_QMGR_QUEUOSTAT0_OFFSET, |
---|
736 | IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD, |
---|
737 | IX_QMGR_UNDERFLOW_BIT_OFFSET, |
---|
738 | TRUE/*reset*/)); |
---|
739 | } |
---|
740 | else |
---|
741 | { |
---|
742 | /* Qs 32-63 have no underflow status */ |
---|
743 | return FALSE; |
---|
744 | } |
---|
745 | } |
---|
746 | |
---|
747 | /* |
---|
748 | * This inline function will read the overflow status of a queue |
---|
749 | * specified by qId. |
---|
750 | */ |
---|
751 | IX_QMGR_AQMIF_INLINE BOOL |
---|
752 | ixQMgrAqmIfOverflowCheck (IxQMgrQId qId) |
---|
753 | { |
---|
754 | if (qId < IX_QMGR_MIN_QUEUPP_QID) |
---|
755 | { |
---|
756 | return (ixQMgrAqmIfRegisterBitCheck (qId, |
---|
757 | IX_QMGR_QUEUOSTAT0_OFFSET, |
---|
758 | IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD, |
---|
759 | IX_QMGR_OVERFLOW_BIT_OFFSET, |
---|
760 | TRUE/*reset*/)); |
---|
761 | } |
---|
762 | else |
---|
763 | { |
---|
764 | /* Qs 32-63 have no overflow status */ |
---|
765 | return FALSE; |
---|
766 | } |
---|
767 | } |
---|
768 | |
---|
769 | /* |
---|
770 | * This inline function will read the status bits of a queue |
---|
771 | * specified by qId. |
---|
772 | */ |
---|
773 | IX_QMGR_AQMIF_INLINE UINT32 |
---|
774 | ixQMgrAqmIfQRegisterBitsRead (IxQMgrQId qId, |
---|
775 | UINT32 registerBaseAddrOffset, |
---|
776 | unsigned queuesPerRegWord) |
---|
777 | { |
---|
778 | volatile UINT32 *registerAddress; |
---|
779 | UINT32 registerWord; |
---|
780 | UINT32 statusBitsMask; |
---|
781 | UINT32 bitsPerQueue; |
---|
782 | |
---|
783 | bitsPerQueue = BITS_PER_WORD / queuesPerRegWord; |
---|
784 | |
---|
785 | /* |
---|
786 | * Calculate the registerAddress |
---|
787 | * multiple queues split accross registers |
---|
788 | */ |
---|
789 | registerAddress = (UINT32*)(aqmBaseAddress + |
---|
790 | registerBaseAddrOffset + |
---|
791 | ((qId / queuesPerRegWord) * |
---|
792 | IX_QMGR_NUM_BYTES_PER_WORD)); |
---|
793 | /* |
---|
794 | * Read the status word |
---|
795 | */ |
---|
796 | ixQMgrAqmIfWordRead (registerAddress, ®isterWord); |
---|
797 | |
---|
798 | |
---|
799 | /* |
---|
800 | * Calculate the mask for the status bits for this queue. |
---|
801 | */ |
---|
802 | statusBitsMask = ((1 << bitsPerQueue) - 1); |
---|
803 | |
---|
804 | /* |
---|
805 | * Shift the status word so it is right justified |
---|
806 | */ |
---|
807 | registerWord >>= ((qId & (queuesPerRegWord - 1)) * bitsPerQueue); |
---|
808 | |
---|
809 | /* |
---|
810 | * Mask out all bar the status bits for this queue |
---|
811 | */ |
---|
812 | return (registerWord &= statusBitsMask); |
---|
813 | } |
---|
814 | |
---|
815 | /* |
---|
816 | * This function is called by IxQMgrDispatcher to set the contents of |
---|
817 | * the AQM interrupt register. |
---|
818 | */ |
---|
819 | IX_QMGR_AQMIF_INLINE void |
---|
820 | ixQMgrAqmIfQInterruptRegWrite (IxQMgrDispatchGroup group, |
---|
821 | UINT32 reg) |
---|
822 | { |
---|
823 | volatile UINT32 *address; |
---|
824 | |
---|
825 | if (group == IX_QMGR_QUELOW_GROUP) |
---|
826 | { |
---|
827 | address = (UINT32*)(aqmBaseAddress + |
---|
828 | IX_QMGR_QINTREG0_OFFSET); |
---|
829 | } |
---|
830 | else |
---|
831 | { |
---|
832 | address = (UINT32*)(aqmBaseAddress + |
---|
833 | IX_QMGR_QINTREG1_OFFSET); |
---|
834 | } |
---|
835 | |
---|
836 | ixQMgrAqmIfWordWrite (address, reg); |
---|
837 | } |
---|
838 | |
---|
839 | /* |
---|
840 | * Read the status of a queue in the range 0-31. |
---|
841 | * |
---|
842 | * This function is used by other QMgr components to read the |
---|
843 | * status of the queue specified by qId. |
---|
844 | */ |
---|
845 | IX_QMGR_AQMIF_INLINE void |
---|
846 | ixQMgrAqmIfQueLowStatRead (IxQMgrQId qId, |
---|
847 | IxQMgrQStatus *status) |
---|
848 | { |
---|
849 | /* Read the general status bits */ |
---|
850 | *status = ixQMgrAqmIfQRegisterBitsRead (qId, |
---|
851 | IX_QMGR_QUELOWSTAT0_OFFSET, |
---|
852 | IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD); |
---|
853 | } |
---|
854 | |
---|
855 | /* |
---|
856 | * This function will read the status of the queue specified |
---|
857 | * by qId. |
---|
858 | */ |
---|
859 | IX_QMGR_AQMIF_INLINE void |
---|
860 | ixQMgrAqmIfQueUppStatRead (IxQMgrQId qId, |
---|
861 | IxQMgrQStatus *status) |
---|
862 | { |
---|
863 | /* Reset the status bits */ |
---|
864 | *status = 0; |
---|
865 | |
---|
866 | /* |
---|
867 | * Check if the queue is nearly empty, |
---|
868 | * N.b. QUPP stat register contains status for regs 32-63 at each |
---|
869 | * bit position so subtract 32 to get bit offset |
---|
870 | */ |
---|
871 | if (ixQMgrAqmIfRegisterBitCheck ((qId - IX_QMGR_MIN_QUEUPP_QID), |
---|
872 | IX_QMGR_QUEUPPSTAT0_OFFSET, |
---|
873 | IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD, |
---|
874 | 0/*relativeBitOffset*/, |
---|
875 | FALSE/*!reset*/)) |
---|
876 | { |
---|
877 | *status |= IX_QMGR_Q_STATUS_NE_BIT_MASK; |
---|
878 | } |
---|
879 | |
---|
880 | /* |
---|
881 | * Check if the queue is full, |
---|
882 | * N.b. QUPP stat register contains status for regs 32-63 at each |
---|
883 | * bit position so subtract 32 to get bit offset |
---|
884 | */ |
---|
885 | if (ixQMgrAqmIfRegisterBitCheck ((qId - IX_QMGR_MIN_QUEUPP_QID), |
---|
886 | IX_QMGR_QUEUPPSTAT1_OFFSET, |
---|
887 | IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD, |
---|
888 | 0/*relativeBitOffset*/, |
---|
889 | FALSE/*!reset*/)) |
---|
890 | { |
---|
891 | *status |= IX_QMGR_Q_STATUS_F_BIT_MASK; |
---|
892 | } |
---|
893 | } |
---|
894 | |
---|
895 | /* |
---|
896 | * This function is used by other QMgr components to read the |
---|
897 | * status of the queue specified by qId. |
---|
898 | */ |
---|
899 | IX_QMGR_AQMIF_INLINE void |
---|
900 | ixQMgrAqmIfQueStatRead (IxQMgrQId qId, |
---|
901 | IxQMgrQStatus *qStatus) |
---|
902 | { |
---|
903 | if (qId < IX_QMGR_MIN_QUEUPP_QID) |
---|
904 | { |
---|
905 | ixQMgrAqmIfQueLowStatRead (qId, qStatus); |
---|
906 | } |
---|
907 | else |
---|
908 | { |
---|
909 | ixQMgrAqmIfQueUppStatRead (qId, qStatus); |
---|
910 | } |
---|
911 | } |
---|
912 | |
---|
913 | |
---|
914 | /* |
---|
915 | * This function performs a mod division |
---|
916 | */ |
---|
917 | IX_QMGR_AQMIF_INLINE unsigned |
---|
918 | ixQMgrAqmIfPow2NumDivide (unsigned numerator, |
---|
919 | unsigned denominator) |
---|
920 | { |
---|
921 | /* Number is evenly divisable by 2 */ |
---|
922 | return (numerator >> ixQMgrAqmIfLog2 (denominator)); |
---|
923 | } |
---|
924 | |
---|
925 | /* Restore IX_COMPONENT_NAME */ |
---|
926 | #undef IX_COMPONENT_NAME |
---|
927 | #define IX_COMPONENT_NAME IX_QMGR_AQMIF_SAVED_COMPONENT_NAME |
---|
928 | |
---|
929 | #endif/*IXQMGRAQMIF_P_H*/ |
---|