source: SVN/cambria/redboot/packages/hal/arm/arch/current/include/hal_mmu.h @ 1

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1#ifndef CYGONCE_HAL_MMU_H
2#define CYGONCE_HAL_MMU_H
3
4//==========================================================================
5//
6//      hal_mmu.h
7//
8//      MMU definitions
9//
10//==========================================================================
11//####ECOSGPLCOPYRIGHTBEGIN####
12// -------------------------------------------
13// This file is part of eCos, the Embedded Configurable Operating System.
14// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15//
16// eCos is free software; you can redistribute it and/or modify it under
17// the terms of the GNU General Public License as published by the Free
18// Software Foundation; either version 2 or (at your option) any later version.
19//
20// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21// WARRANTY; without even the implied warranty of MERCHANTABILITY or
22// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
23// for more details.
24//
25// You should have received a copy of the GNU General Public License along
26// with eCos; if not, write to the Free Software Foundation, Inc.,
27// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28//
29// As a special exception, if other files instantiate templates or use macros
30// or inline functions from this file, or you compile this file and link it
31// with other works to produce a work based on this file, this file does not
32// by itself cause the resulting work to be covered by the GNU General Public
33// License. However the source code for this file must still be made available
34// in accordance with section (3) of the GNU General Public License.
35//
36// This exception does not invalidate any other reasons why a work based on
37// this file might be covered by the GNU General Public License.
38//
39// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40// at http://sources.redhat.com/ecos/ecos-license/
41// -------------------------------------------
42//####ECOSGPLCOPYRIGHTEND####
43//==========================================================================
44//#####DESCRIPTIONBEGIN####
45//
46// Author(s):    gthomas
47// Contributors: gthomas
48// Date:         1999-05-10
49// Purpose:      Define MMU for ARM
50// Usage:        #include <cyg/hal/hal_mmu.h>
51
52//             
53//####DESCRIPTIONEND####
54//
55//==========================================================================
56
57#define MMU_L1_TYPE         0x03  // Descriptor type
58#define MMU_L1_TYPE_Fault   0x00  // Invalid
59#define MMU_L1_TYPE_Page    0x11  // Individual page mapping
60#define MMU_L1_TYPE_Section 0x12  // Mapping for 1M segment
61
62#define MMU_L2_TYPE         0x03  // Descriptor type
63#define MMU_L2_TYPE_Fault   0x00  // Invalid data
64#define MMU_L2_TYPE_Large   0x01  // Large page (64K)
65#define MMU_L2_TYPE_Small   0x02  // Small page (4K)
66
67#define MMU_Bufferable      0x04  // Data can use write-buffer
68#define MMU_Cacheable       0x08  // Data can use cache
69
70#define MMU_AP_Limited     0x000  // Limited access
71#define MMU_AP_Supervisor  0x400  // Supervisor RW, User none
72#define MMU_AP_UserRead    0x800  // Supervisor RW, User read only
73#define MMU_AP_Any         0xC00  // Supervisor RW, User RW
74
75#define MMU_AP_ap0_Any     0x030
76#define MMU_AP_ap1_Any     0x0C0
77#define MMU_AP_ap2_Any     0x300
78#define MMU_AP_ap3_Any     0xC00
79#define MMU_AP_All (MMU_AP_ap0_Any|MMU_AP_ap1_Any|MMU_AP_ap2_Any|MMU_AP_ap3_Any)
80
81#define MMU_DOMAIN(x)      ((x)<<5)
82
83#define MMU_PAGE_SIZE      0x1000
84#define MMU_SECTION_SIZE   0x100000
85
86#define MMU_CP               p15      // Co-processor ID
87#define MMU_Control          c1       // Control register
88#define MMU_Base             c2       // Page tables base
89#define MMU_DomainAccess     c3       // Domain access control
90#define MMU_FaultStatus      c5       // Fault status register
91#define MMU_FaultAddress     c6       // Fault Address
92#define MMU_InvalidateCache  c7       // Invalidate cache data
93#define MMU_TLB              c8       // Translation Lookaside Buffer
94
95// These seem to be 710 specific
96#define MMU_FlushTLB         c5
97#define MMU_FlushIDC         c7
98
99#define MMU_Control_M  0x001    // Enable MMU
100#define MMU_Control_A  0x002    // Enable address alignment faults
101#define MMU_Control_C  0x004    // Enable cache
102#define MMU_Control_W  0x008    // Enable write-buffer
103#define MMU_Control_P  0x010    // Compatability: 32 bit code
104#define MMU_Control_D  0x020    // Compatability: 32 bit data
105#define MMU_Control_L  0x040    // Compatability:
106#define MMU_Control_B  0x080    // Enable Big-Endian
107#define MMU_Control_S  0x100    // Enable system protection
108#define MMU_Control_R  0x200    // Enable ROM protection
109#define MMU_Control_I  0x1000   // Enable Instruction cache
110#define MMU_Control_X  0x2000   // Set interrupt vectors at 0xFFFF0000
111#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
112
113// Extras for some newer versions eg. ARM920 with architecture version 4.
114#define MMU_Control_F  0x400    // IMPLEMENTATION DEFINED
115#define MMU_Control_Z  0x800    // Enable branch predicion
116#define MMU_Control_RR 0x4000   // Select non-random cache replacement
117
118//-----------------------------------------------------------------------------
119
120#endif // CYGONCE_HAL_MMU_H
121// End of hal_mmu.h
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