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1#ifndef CYGONCE_PCI_H
2#define CYGONCE_PCI_H
3//=============================================================================
4//
5//      pci.h
6//
7//      PCI library
8//
9//=============================================================================
10//####ECOSGPLCOPYRIGHTBEGIN####
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41//####ECOSGPLCOPYRIGHTEND####
42//=============================================================================
43//#####DESCRIPTIONBEGIN####
44//
45// Author(s):    jskov, from design by nickg
46// Contributors: jskov
47// Date:         1999-08-09
48// Purpose:      PCI configuration access
49// Usage:
50//              #include <cyg/io/pci.h>
51// Description:
52//             This library provides a set of routines for accessing
53//             the PCI bus configuration space in a portable manner.
54//             This is provided by two APIs. The high level API (defined
55//             by this file) is used by device drivers, or other code, to
56//             access the PCI configuration space portably. The low level
57//             API (see pci_hw.h) is used  by the PCI library itself
58//             to access the hardware in a platform-specific manner and
59//             may also be used by device drivers to access the PCI
60//             configuration space directly.
61//
62//####DESCRIPTIONEND####
63//
64//=============================================================================
65
66#include <cyg/infra/cyg_type.h>
67#include <cyg/io/pci_cfg.h>
68#include <cyg/io/pci_hw.h>
69
70//------------------------------------------------------------------
71// Map a logical (CPU local) address to one used by a PCI master
72// Normally, this is just the physical address of the object, but
73// it may differ if the platform has different address maps from
74// the CPU side vs. the PCI side
75#ifndef CYGARC_PCI_DMA_ADDRESS
76#define CYGARC_PCI_DMA_ADDRESS(_x_) CYGARC_PHYSICAL_ADDRESS(_x_)
77#endif
78
79//------------------------------------------------------------------
80// The PCI memory space can span 64 bits, IO space only 32 bits
81typedef CYG_WORD64 CYG_PCI_ADDRESS64;
82typedef CYG_WORD32 CYG_PCI_ADDRESS32;
83
84//------------------------------------------------------------------
85// Macros for manufacturing and decomposing device ids
86typedef CYG_WORD32 cyg_pci_device_id;           // PCI device ID
87
88#define CYG_PCI_DEV_MAKE_ID(__bus,__devfn) (((__bus)<<16)|((__devfn)<<8))
89#define CYG_PCI_DEV_GET_BUS(__devid) ((__devid>>16)&0xFF)
90#define CYG_PCI_DEV_GET_DEVFN(__devid) ((__devid>>8)&0xFF)
91
92#define CYG_PCI_NULL_DEVID 0xffffffff
93#define CYG_PCI_NULL_DEVFN 0xffff
94
95//------------------------------------------------------------------
96// PCI device data definitions and structures
97
98typedef enum { 
99    CYG_PCI_HEADER_NORMAL = 0, 
100    CYG_PCI_HEADER_BRIDGE = 1,
101    CYG_PCI_HEADER_CARDBUS_BRIDGE = 2
102} cyg_pci_header_type;
103
104typedef struct                          // PCI device data
105{
106    cyg_pci_device_id devid;            // ID of this device
107
108    // The following fields are read out of the
109    // config space for this device.
110
111    cyg_uint16  vendor;                 // vendor ID
112    cyg_uint16  device;                 // device ID
113    cyg_uint16  command;                // command register
114    cyg_uint16  status;                 // status register
115    cyg_uint32  class_rev;              // class+revision
116    cyg_uint8   cache_line_size;        // cache line size
117    cyg_uint8   latency_timer;          // latency timer
118    cyg_pci_header_type header_type;    // header type
119    cyg_uint8   bist;                   // Built-in Self-Test
120    cyg_uint32  base_address[6];        // Memory base address registers
121
122    // The following fields are used by the resource allocation
123    // routines to keep track of allocated resources.
124    cyg_uint32 num_bars;
125       
126    cyg_uint32 base_size[6];            // Memory size for each base address
127    cyg_uint32 base_map[6];             // Physical address mapped
128
129    CYG_ADDRWORD hal_vector;            // HAL interrupt vector used by
130                                        // device if int_line!=0
131
132    // One of the following unions will be filled in according to
133    // the value of the header_type field.
134
135    union
136    {
137        struct
138        {
139            cyg_uint32  cardbus_cis;    // CardBus CIS Pointer
140            cyg_uint16  sub_vendor;     // subsystem vendor id
141            cyg_uint16  sub_id;         // subsystem id
142            cyg_uint32  rom_address;    // ROM address register
143            cyg_uint8   cap_list;       // capability list
144            cyg_uint8   reserved1[7];
145            cyg_uint8   int_line;       // interrupt line
146            cyg_uint8   int_pin;        // interrupt pin
147            cyg_uint8   min_gnt;        // timeslice request
148            cyg_uint8   max_lat;        // priority-level request
149        } normal;
150        struct
151        {
152            cyg_uint8   pri_bus;                // primary bus number
153            cyg_uint8   sec_bus;                // secondary bus number
154            cyg_uint8   sub_bus;                // subordinate bus number
155            cyg_uint8   sec_latency_timer;      // secondary bus latency
156            cyg_uint8   io_base;
157            cyg_uint8   io_limit;
158            cyg_uint16  sec_status;             // secondary bus status
159            cyg_uint16  mem_base;
160            cyg_uint16  mem_limit;
161            cyg_uint16  prefetch_base;
162            cyg_uint16  prefetch_limit;
163            cyg_uint32  prefetch_base_upper32;
164            cyg_uint32  prefetch_limit_upper32; 
165            cyg_uint16  io_base_upper16;
166            cyg_uint16  io_limit_upper16;
167            cyg_uint8   reserved1[4];
168            cyg_uint32  rom_address;            // ROM address register
169            cyg_uint8   int_line;               // interrupt line
170            cyg_uint8   int_pin;                // interrupt pin
171            cyg_uint16  control;                // bridge control
172        } bridge;
173        struct
174        {
175            // Not yet supported
176        } cardbus_bridge;
177    } header;
178} cyg_pci_device;
179   
180//------------------------------------------------------------------------
181// Init
182externC void cyg_pci_init( void );
183
184//------------------------------------------------------------------------
185// Common device configuration access functions
186
187// This function gets the PCI configuration information for the
188// device indicated in devid. The common fields of the cyg_pci_device
189// structure, and the appropriate fields of the relevant header union
190// member are filled in from the device's configuration space. If the
191// device has not been enabled, then this function will also fetch
192// the size and type information from the base address registers and
193// place it in the base_size[] array.
194externC void cyg_pci_get_device_info ( cyg_pci_device_id devid, 
195                                        cyg_pci_device *dev_info );
196
197
198// This function sets the PCI configuration information for the
199// device indicated in devid. Only the configuration space registers
200// that are writable are actually written. Once all the fields have
201// been written, the device info will be read back into *dev_info, so
202// that it reflects the true state of the hardware.
203externC void cyg_pci_set_device_info ( cyg_pci_device_id devid, 
204                                       cyg_pci_device *dev_info );
205
206//------------------------------------------------------------------------
207// Device find functions
208
209// Searches the PCI bus configuration space for a device with the
210// given vendor and device ids. The search starts at the device
211// pointed to by devid, or at the first slot if it contains
212// CYG_PCI_NULL_DEVID. *devid will be updated with the ID of the next
213// device found. Returns true if one is found and false if not.
214externC cyg_bool cyg_pci_find_device( cyg_uint16 vendor, cyg_uint16 device,
215                                      cyg_pci_device_id *devid );
216
217
218// Searches the PCI bus configuration space for a device with the
219// given class code.  The search starts at the device pointed to by
220// devid, or at the first slot if it contains CYG_PCI_NULL_DEVID.
221// *devid will be updated with the ID of the next device found.
222// Returns true if one is found and false if not.
223externC cyg_bool cyg_pci_find_class( cyg_uint32 dev_class,
224                                     cyg_pci_device_id *devid );
225
226
227
228// Searches the PCI bus configuration space for a device whose properties
229// match those required by the match_func, which the user supplies.  The
230// match_func's arguments are vendor, device, class exactly as they might
231// be in the two APIs above.  The additional parameter is for any state
232// which a caller might wish available to its callback routine.
233// The search starts at the device pointed to by
234// devid, or at the first slot if it contains CYG_PCI_NULL_DEVID.  *devid
235// will be updated with the ID of the next device found.  Returns true if
236// one is found and false if not.
237typedef cyg_bool (cyg_pci_match_func)( cyg_uint16,/* vendor */
238                                       cyg_uint16,/* device */
239                                       cyg_uint32,/* class  */
240                                       void * /* arbitrary user data */ );
241externC cyg_bool cyg_pci_find_matching( cyg_pci_match_func *matchp,
242                                        void * match_callback_data,
243                                        cyg_pci_device_id *devid );
244
245
246// Searches the PCI configuration space for the next valid device
247// after cur_devid. If cur_devid is given the value
248// CYG_PCI_NULL_DEVID, then the search starts at the first slot. It
249// is permitted for next_devid to point to the cur_devid.  Returns
250// true if another device is found and false if not.
251externC cyg_bool cyg_pci_find_next( cyg_pci_device_id cur_devid, 
252                                    cyg_pci_device_id *next_devid );
253
254//------------------------------------------------------------------------
255// Resource Allocation
256// These routines allocate memory and IO space to PCI devices.
257
258// Allocate memory and IO space to all base address registers using
259// the current memory and IO base addresses in the library. If
260// dev_info does not contain valid base_size[] entries, then the
261// result is false.
262externC cyg_bool cyg_pci_configure_device( cyg_pci_device *dev_info );
263
264// Allocate memory and IO space for all devices found on the given
265// bus and its subordinate busses. This routine recurses when a
266// PCI-to-PCI bridge is encountered. The next_bus argument points
267// to a variable holding the bus number of the next PCI bus to
268// be allocated when a bridge is encountered. This routine returns
269// true if successful, false if unsuccessful.
270externC cyg_bool cyg_pci_configure_bus( cyg_uint8 bus,
271                                        cyg_uint8 *next_bus );
272
273// These routines set the base addresses for memory and IO mappings
274// to be used by the memory allocation routines. Normally these base
275// addresses will be set to default values based on the platform,
276// these routines allow those to be changed by application code if
277// necessary.
278externC void cyg_pci_set_memory_base( CYG_PCI_ADDRESS64 base );
279externC void cyg_pci_set_io_base( CYG_PCI_ADDRESS32 base );
280
281// These routines allocate memory or IO space to the base address
282// register indicated by bar. The base address in *base will be
283// correctly aligned and the address of the next free location will
284// be written back into it if the allocation succeeds. If the base
285// address register is of the wrong type for this allocation, or
286// dev_info does not contain valid base_size[] entries, the result is
287// false.
288externC cyg_bool cyg_pci_allocate_memory( cyg_pci_device *dev_info,
289                                          cyg_uint32 bar, 
290                                          CYG_PCI_ADDRESS64 *base );
291externC cyg_bool cyg_pci_allocate_io( cyg_pci_device *dev_info,
292                                      cyg_uint32 bar, 
293                                      CYG_PCI_ADDRESS32 *base );
294
295// Translate the device's PCI interrupt (INTA#-INTD#) to the
296// associated HAL vector. This may also depend on which slot the
297// device occupies. If the device may generate interrupts, the
298// translated vector number will be stored in vec and the result is
299// true. Otherwise the result is false.
300externC cyg_bool cyg_pci_translate_interrupt( cyg_pci_device *dev_info,
301                                              CYG_ADDRWORD *vec );
302
303
304//----------------------------------------------------------------------
305// Specific device configuration access functions
306
307// Read functions
308// These functions read registers of the appropriate size from the
309// configuration space of the given device. They should mainly be
310// used to access registers that are device specific. General PCI
311// registers are best accessed through cyg_pci_get_device_info().
312externC void cyg_pci_read_config_uint8( cyg_pci_device_id devid,
313                                        cyg_uint8 offset, cyg_uint8 *val);
314externC void cyg_pci_read_config_uint16( cyg_pci_device_id devid,
315                                         cyg_uint8 offset, cyg_uint16 *val);
316externC void cyg_pci_read_config_uint32( cyg_pci_device_id devid,
317                                         cyg_uint8 offset, cyg_uint32 *val);
318
319// Write functions
320// These functions write registers of the appropriate size to the
321// configuration space of the given device. They should mainly be
322// used to access registers that are device specific. General PCI
323// registers are best accessed through
324// cyg_pci_get_device_info(). Writing the general registers this way
325// may render the contents of a cyg_pci_device structure invalid.
326externC void cyg_pci_write_config_uint8( cyg_pci_device_id devid,
327                                         cyg_uint8 offset, cyg_uint8 val);
328externC void cyg_pci_write_config_uint16( cyg_pci_device_id devid,
329                                          cyg_uint8 offset, cyg_uint16 val);
330externC void cyg_pci_write_config_uint32( cyg_pci_device_id devid,
331                                          cyg_uint8 offset, cyg_uint32 val);
332
333
334//----------------------------------------------------------------------
335// Functions private to the PCI library. These should only be used by
336// tests.
337externC cyg_bool cyg_pci_allocate_memory_priv(cyg_pci_device *dev_info,
338                                              cyg_uint32 bar,
339                                              CYG_PCI_ADDRESS64 *base,
340                                             CYG_PCI_ADDRESS64 *assigned_addr);
341externC cyg_bool cyg_pci_allocate_io_priv( cyg_pci_device *dev_info,
342                                           cyg_uint32 bar, 
343                                           CYG_PCI_ADDRESS32 *base,
344                                           CYG_PCI_ADDRESS32 *assigned_addr);
345
346
347//----------------------------------------------------------------------
348// Bus probing limits.
349// Note: these can be overridden by the platform
350#ifndef CYG_PCI_MAX_BUS
351#define CYG_PCI_MAX_BUS                      8  // Eight is enough?
352#endif
353#ifndef CYG_PCI_MAX_DEV
354#define CYG_PCI_MAX_DEV                      32
355#endif
356#ifndef CYG_PCI_MIN_DEV
357#define CYG_PCI_MIN_DEV                      0
358#endif
359#ifndef CYG_PCI_MAX_FN
360#define CYG_PCI_MAX_FN                       8
361#endif
362#ifndef CYG_PCI_MAX_BAR
363#define CYG_PCI_MAX_BAR                      6
364#endif
365
366//-----------------------------------------------------------------------------
367#endif // ifndef CYGONCE_PCI_H
368// End of pci.h
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