source: SVN/laguna/u-boot-2008.10/include/configs/cavium_cns3000.h @ 57

Last change on this file since 57 was 57, checked in by Tim Harvey, 2 years ago

Laguna: move prebuilt images and bootloader

svn directory cleanup

File size: 7.8 KB
Line 
1/*
2 * (C) Copyright 2003
3 * Texas Instruments.
4 * Kshitij Gupta <kshitij@ti.com>
5 * Configuation settings for the TI OMAP Innovator board.
6 *
7 * (C) Copyright 2004
8 * ARM Ltd.
9 * Philippe Robin, <philippe.robin@arm.com>
10 * Configuration for Versatile PB.
11 *
12 * (C) Copyright 2008
13 * Cavium Networks Ltd.
14 * Scott Shu <scott.shu@caviumnetworks.com>
15 * Configuration for Cavium Networks CNS3000 Platform
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 */
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38/*
39 *  Code, etc. common to all ARM supplied development boards
40 */
41#include <armsupplied.h>
42
43/*
44 * Board info register
45 */
46#define SYS_ID  (0x10000000)
47#define ARM_SUPPLIED_REVISION_REGISTER SYS_ID
48
49/*
50 * High Level Configuration Options
51 * (easy to change)
52 */
53#define CONFIG_CNS3000          1               /* in a Cavium Networks CNS3000 SoC */
54
55#define CONFIG_DISPLAY_CPUINFO  1               /* display cpu info */
56#define CONFIG_DISPLAY_BOARDINFO 1              /* display board info */
57
58#define CFG_MEMTEST_START       0x100000
59#define CFG_MEMTEST_END         0x10000000
60
61#define CFG_HZ                  (1000)
62#define CFG_HZ_CLOCK            1000000         /* Timers clocked at 1Mhz */
63#define CFG_TIMERBASE           0x7C800000      /* Timer 1 base */
64#define CFG_TIMER_RELOAD        0xFFFFFFFF
65#define TIMER_LOAD_VAL          CFG_TIMER_RELOAD
66
67#define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs      */
68#define CONFIG_SETUP_MEMORY_TAGS        1
69#define CONFIG_MISC_INIT_R
70
71/*
72 * Size of malloc() pool
73 */
74/* scott.check */
75#define CFG_MALLOC_LEN          (CONFIG_ENV_SIZE + 512*1024)
76#define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
77
78/*
79 * Hardware drivers
80 */
81#define GPIOA_PERST                     11
82
83/*
84 * NS16550 Configuration
85 */
86# define CFG_SERIAL0            0x78000000
87# define CFG_SERIAL1            0x78400000
88# define CFG_SERIAL2            0x78800000
89# define CFG_SERIAL3            0x78C00000
90
91/*
92 * select serial console configuration
93 */
94#define CONFIG_CNS3000_SERIAL
95#define CONFIG_CNS3000_CLOCK    24000000
96#define CONFIG_CNS3000_PORTS    { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, (void *)CFG_SERIAL2 }
97#define CONFIG_CONS_INDEX       0
98
99#define CONFIG_BAUDRATE         115200
100#define CFG_BAUDRATE_TABLE      { 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
101#define CFG_CONSOLE_INFO_QUIET
102#define CONFIG_CMDLINE_EDITING
103
104/* allow to overwrite serial and ethaddr */
105#define CONFIG_ENV_OVERWRITE
106
107/*
108 * I2C
109 */
110#define CONFIG_DRIVER_CNS3XXX_I2C
111#define CONFIG_HARD_I2C     /* I2C with hardware support  */
112#undef  CONFIG_SOFT_I2C     /* I2C bit-banged   */
113#define CFG_I2C_SPEED   100000  /* I2C speed and slave address  */
114#define CFG_I2C_SLAVE   0x7f /* UNUSED */
115
116#define CFG_I2C_EEPROM_ADDR 0x50    /* base address */
117#define CFG_I2C_EEPROM_ADDR_LEN 1   /* bytes of address */
118/* mask of address bits that overflow into the "EEPROM chip address"    */
119#define CFG_I2C_EEPROM_ADDR_OVERFLOW  0x07
120#define CFG_EEPROM_PAGE_WRITE_BITS  3 /* 8 byte write page size */
121#define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10  /* and takes up to 10 msec */
122
123
124/*
125 * Real Time Clock
126 */
127#define CONFIG_RTC_CNS3000      1
128
129/*
130 * MMC/SD Host Controller
131 */
132#define CONFIG_CNS3000_MMC      1
133#ifdef CONFIG_CNS3000_MMC
134#define CONFIG_MMC              1
135#define CONFIG_DOS_PARTITION    1
136#endif
137
138/*
139 * Command line configuration.
140 */
141#include <config_cmd_default.h>
142#define CONFIG_CMD_ASKENV
143#define CONFIG_CMD_DIAG
144#define CONFIG_CMD_EEPROM
145#define CONFIG_CMD_JFFS2
146#define CONFIG_CMD_DHCP
147#define CONFIG_CMD_PING
148#define CONFIG_CMD_CACHE
149#define CONFIG_CMD_ELF
150#define CONFIG_CMD_I2C
151#define CONFIG_CMD_SAVES
152#undef CONFIG_CMD_FPGA
153#undef CONFIG_CMD_SETGETDCR
154
155#ifdef CONFIG_RTC_CNS3000
156#define CONFIG_CMD_DATE
157#endif
158
159#ifdef CONFIG_CNS3000_MMC
160#define CONFIG_CMD_MMC
161#define CONFIG_CMD_FAT
162#endif
163
164#define CONFIG_BOOTDELAY        2
165
166#define CONFIG_UDP_FRAGMENT     1
167
168#ifdef CONFIG_UDP_FRAGMENT
169#define CONFIG_EXTRA_ENV_SETTINGS       \
170        "tftp_bsize=512\0"              \
171        "udp_frag_size=512\0"
172#endif
173
174/*
175The kernel command line & boot command below are for a Cavium Networks CNS3000 board
1760x00000000  u-boot
1770x0000????  knuxernel
1780x0000????  Root File System
179*/
180
181#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/mtdblock3 rootfstype=squashfs,jffs2 noinitrd init=/etc/preinit"
182#define CONFIG_BOOTCOMMAND "bootm 0x10060000"
183
184#define CONFIG_NET_MULTI
185#define CONFIG_HAS_ETH1
186#define CONFIG_HAS_ETH2
187#define CONFIG_HAS_ETH3
188
189#define ENV_ETH_PRIME     "eth0"
190
191/*
192 * Static configuration when assigning fixed address
193 */
194#define CONFIG_NETMASK          255.255.0.0             /* talk on MY local net */
195#define CONFIG_IPADDR                   192.168.1.211           /* static IP I currently own */
196#define CONFIG_SERVERIP         192.168.1.14            /* current IP of my dev pc */
197
198/*
199 * Miscellaneous configurable options
200 */
201#define CFG_LONGHELP                            /* undef to save memory          */
202#define CFG_PROMPT              "Laguna > "
203#define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
204/* Print Buffer Size */
205#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
206#define CFG_MAXARGS             16              /* max number of command args    */
207#define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size            */
208
209#undef  CFG_CLKS_IN_HZ                          /* everything, incl board info, in Hz */
210#define CFG_LOAD_ADDR           0x00800000      /* default load address */
211
212/*-----------------------------------------------------------------------
213 * Stack sizes
214 *
215 * The stack sizes are set up in start.S using the settings below
216 */
217#define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
218#ifdef CONFIG_USE_IRQ
219#define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
220#define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
221#endif
222
223/*-----------------------------------------------------------------------
224 * Physical Memory Map
225 */
226#define PHYS_SDRAM_32BIT                                        /* undefined: 16 bits, defined: 32 bits */
227// #undef PHYS_SDRAM_32BIT                                      /* undefined: 16 bits, defined: 32 bits */
228
229#define CONFIG_NR_DRAM_BANKS            1               /* we have 1 bank of DRAM */
230#define PHYS_SDRAM_1                    0x20000000      /* SDRAM Bank #1 */
231
232#ifdef PHYS_SDRAM_32BIT
233#define PHYS_SDRAM_1_SIZE               0x8000000       /* 0x10000000 = 256 MB */
234#else
235#define PHYS_SDRAM_1_SIZE               0x08000000      /* 0x08000000 = 128 MB */
236#endif
237
238/*-----------------------------------------------------------------------
239 * FLASH and environment organization
240 */
241/*
242 *  Use the CFI flash driver for ease of use
243 */
244#define PHYS_FLASH_1                                            0x10000000
245#define CFG_FLASH_USE_BUFFER_WRITE 1
246
247#define CFG_FLASH_BASE                  PHYS_FLASH_1
248#define CFG_MONITOR_BASE                CFG_MONITOR_BASE
249#define CFG_MONITOR_LEN                 (256 << 10)
250
251#define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
252#define CFG_MAX_FLASH_SECT      256 /* max number of sectors on one chip    */
253
254#define CFG_FLASH_CFI       /* The flash is CFI compatible  */
255#define CONFIG_FLASH_CFI_DRIVER     /* Use common CFI driver  */
256#define CONFIG_ENV_IS_IN_FLASH  1
257
258#define CFG_FLASH_BANKS_LIST  { PHYS_FLASH_1 }
259
260#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes */
261
262#define CFG_FLASH_EMPTY_INFO    /* print 'E' for empty sector on flinfo */
263
264#define CONFIG_ENV_SECT_SIZE  0x20000 /* size of one complete sector  */
265#define CONFIG_ENV_ADDR   (PHYS_FLASH_1 + 0x40000)
266#define CONFIG_ENV_SIZE   0x20000  /* Total Size of Environment Sector */
267
268#define CFG_SPI_FLASH_BASE    0x60000000
269
270#define CFG_MAX_DATAFLASH_BANKS   1
271#define CFG_DATAFLASH_LOGIC_ADDR_CS0  CFG_SPI_FLASH_BASE  /* Logical adress for CS0 */
272
273#endif /* __CONFIG_H */
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