source: SVN/rincon/u-boot/board/MAI/AmigaOneG3SE/via686.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 8.5 KB
Line 
1/*
2 * (C) Copyright 2002
3 * Hyperion Entertainment, Hans-JoergF@hyperion-entertainment.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23#include <common.h>
24#include <pci.h>
25#include <ata.h>
26#include "memio.h"
27#include "articiaS.h"
28#include "via686.h"
29#include "i8259.h"
30
31DECLARE_GLOBAL_DATA_PTR;
32
33#undef VIA_DEBUG
34
35#ifdef  VIA_DEBUG
36#define PRINTF(fmt,args...)     printf (fmt ,##args)
37#else
38#define PRINTF(fmt,args...)
39#endif
40
41
42/*  Setup the ISA-to-PCI host bridge */
43void via_isa_init(pci_dev_t dev, struct pci_config_table *table)
44{
45    char regval;
46    if (PCI_FUNC(dev) == 0)
47    {
48        PRINTF("... PCI-to-ISA bridge, dev=0x%X\n", dev);
49
50        /*  Enable I/O Recovery time */
51        pci_write_config_byte(dev, 0x40, 0x08);
52
53        /*  Enable ISA refresh */
54        pci_write_config_byte(dev, 0x41, 0x41); /*  was 01 */
55
56        /*  Enable ISA line buffer */
57        pci_write_config_byte(dev, 0x45, 0x80);
58
59        /*  Gate INTR, and flush line buffer */
60        pci_write_config_byte(dev, 0x46, 0x60);
61
62        /*  Enable EISA ports 4D0/4D1. Do we need this ? */
63        pci_write_config_byte(dev, 0x47, 0xe6); /*  was 20 */
64
65        /*  512 K PCI Decode */
66        pci_write_config_byte(dev, 0x48, 0x01);
67
68        /*  Wait for PGNT before grant to ISA Master/DMA */
69        /*  ports 0-FF to SDBus */
70        /*  IRQ 14 and 15 for ide 0/1 */
71        pci_write_config_byte(dev, 0x4a, 0x04); /*  Was c4 */
72
73        /*  Plug'n'Play */
74        /*  Parallel DRQ 3, Floppy DRQ 2 (default) */
75        pci_write_config_byte(dev, 0x50, 0x0e);
76
77        /*  IRQ Routing for Floppy and Parallel port */
78        /*  IRQ 6 for floppy, IRQ 7 for parallel port */
79        pci_write_config_byte(dev, 0x51, 0x76);
80
81        /*  IRQ Routing for serial ports (take IRQ 3 and 4) */
82        pci_write_config_byte(dev, 0x52, 0x34);
83
84        /*  All IRQ's level triggered. */
85        pci_write_config_byte(dev, 0x54, 0x00);
86
87        /*  PCI IRQ's all at IRQ 9 */
88        pci_write_config_byte(dev, 0x55, 0x90);
89        pci_write_config_byte(dev, 0x56, 0x99);
90        pci_write_config_byte(dev, 0x57, 0x90);
91
92        /*  Enable Keyboard */
93        pci_read_config_byte(dev, 0x5A, &regval);
94        regval |= 0x01;
95        pci_write_config_byte(dev, 0x5A, regval);
96
97        pci_write_config_byte(dev, 0x80, 0);
98        pci_write_config_byte(dev, 0x85, 0x01);
99
100/*      pci_write_config_byte(dev, 0x77, 0x00); */
101    }
102}
103
104/*
105 * Initialize PNP irq routing
106 */
107
108void via_init_irq_routing(uint8 irq_map[])
109{
110    char *s;
111    uint8 level_edge_bits = 0xf;
112
113    /* Set irq routings */
114    pci_write_cfg_byte(0, 7<<3, 0x55, irq_map[0]<<4);
115    pci_write_cfg_byte(0, 7<<3, 0x56, irq_map[1] | irq_map[2]<<4);
116    pci_write_cfg_byte(0, 7<<3, 0x57, irq_map[3]<<4);
117
118    /*
119     * Gather level/edge bits
120     * Default is to assume level triggered
121     */
122
123    s = getenv("pci_irqa_select");
124    if (s && strcmp(s, "level") == 0)
125        level_edge_bits &= ~0x01;
126
127    s = getenv("pci_irqb_select");
128    if (s && strcmp(s, "level") == 0)
129        level_edge_bits &= ~0x02;
130
131    s = getenv("pci_irqc_select");
132    if (s && strcmp(s, "level") == 0)
133        level_edge_bits &= ~0x04;
134
135    s = getenv("pci_irqd_select");
136    if (s && strcmp(s, "level") == 0)
137        level_edge_bits &= ~0x08;
138
139    PRINTF("IRQ map\n");
140    PRINTF("%d: %s\n", irq_map[0], level_edge_bits&0x1 ? "edge" : "level");
141    PRINTF("%d: %s\n", irq_map[1], level_edge_bits&0x2 ? "edge" : "level");
142    PRINTF("%d: %s\n", irq_map[2], level_edge_bits&0x4 ? "edge" : "level");
143    PRINTF("%d: %s\n", irq_map[3], level_edge_bits&0x8 ? "edge" : "level");
144    pci_write_cfg_byte(0, 7<<3, 0x54, level_edge_bits);
145
146    PRINTF("%02x %02x %02x %02x\n", pci_read_cfg_byte(0, 7<<3, 0x54),
147           pci_read_cfg_byte(0, 7<<3, 0x55), pci_read_cfg_byte(0, 7<<3, 0x56),
148           pci_read_cfg_byte(0, 7<<3, 0x57));
149}
150
151
152/*  Setup the IDE controller. This doesn't seem to work yet. I/O to an IDE controller port */
153/*  always return the last character output on the serial port (!) */
154/*  This function is called by the pnp-library when it encounters 0:7:1 */
155void via_cfgfunc_ide_init(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table)
156{
157    PRINTF("... IDE controller, dev=0x%X\n", dev);
158
159    /*  Enable both IDE channels. */
160    pci_write_config_byte(dev, 0x40, 0x03);
161    /*  udelay(10000); */
162    /*  udelay(10000); */
163
164    /*  Enable IO Space */
165    pci_write_config_word(dev, 0x04, 0x03);
166
167    /*  Set to compatibility mode */
168    pci_write_config_byte(dev, 0x09, 0x8A); /*  WAS: 0x8f); */
169
170    /*  Set to legacy interrupt mode */
171    pci_write_config_byte(dev, 0x3d, 0x00); /* WAS: 0x01); */
172
173}
174
175
176/*  Set the base address of the floppy controller to 0x3F0 */
177void via_fdc_init(pci_dev_t dev)
178{
179    unsigned char c;
180    /*  Enable Configuration mode */
181    pci_read_config_byte(dev, 0x85, &c);
182    c |= 0x02;
183    pci_write_config_byte(dev, 0x85, c);
184
185    /*  Set floppy controller port to 0x3F0. */
186    SIO_WRITE_CONFIG(0xE3, (0x3F<<2));
187
188    /*  Enable floppy controller */
189    SIO_READ_CONFIG(0xE2, c);
190    c |= 0x10;
191    SIO_WRITE_CONFIG(0xE2, c);
192
193    /*  Switch of configuration mode */
194    pci_read_config_byte(dev, 0x85, &c);
195    c &= ~0x02;
196    pci_write_config_byte(dev, 0x85, c);
197}
198
199/*  Init function 0 of the via southbridge. Called by the pnp-library */
200void via_cfgfunc_via686(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table)
201{
202    if (PCI_FUNC(dev) == 0)
203    {
204        /* FIXME: Try to generate a PCI reset */
205        /* unsigned char c; */
206        /* pci_read_config_byte(dev, 0x47, &c); */
207        /* pci_write_config_byte(dev, 0x47, c | 0x01); */
208
209        via_isa_init(dev, table);
210        via_fdc_init(dev);
211    }
212}
213
214__asm         ("    .globl via_calibrate_time_base \n"
215               "via_calibrate_time_base:           \n"
216               "   lis     9, 0xfe00               \n"
217               "   li      0, 0x00                 \n"
218               "   mttbu   0                       \n"
219               "   mttbl   0                       \n"
220               "ctb_loop:                          \n"
221               "   lbz     0, 0x61(9)              \n"
222               "   eieio                           \n"
223               "   andi.   0, 0, 0x20              \n"
224               "   beq     ctb_loop                \n"
225               "ctb_done:                          \n"
226               "   mftb    3                       \n"
227               "   blr");
228
229extern unsigned long via_calibrate_time_base(void);
230
231void via_calibrate_bus_freq (void)
232{
233        unsigned long tb;
234
235        /* This is 20 microseconds */
236#define CALIBRATE_TIME 28636
237
238        /* Enable the timer (and disable speaker) */
239        unsigned char c;
240
241        c = in_byte (0x61);
242        out_byte (0x61, ((c & ~0x02) | 0x01));
243
244        /* Set timer 2 to low/high writing */
245        out_byte (0x43, 0xb0);
246        out_byte (0x42, CALIBRATE_TIME & 0xff);
247        out_byte (0x42, CALIBRATE_TIME >> 8);
248
249        /* Read the time base */
250        tb = via_calibrate_time_base ();
251
252        if (tb >= 700000)
253                gd->bus_clk = 133333333;
254        else
255                gd->bus_clk = 100000000;
256
257}
258
259
260void ide_led(uchar led, uchar status)
261{
262/*     unsigned char c = in_byte(0x92); */
263
264/*     if (!status) */
265/*      out_byte(0x92, c | 0xC0); */
266/*     else */
267/*      out_byte(0x92, c & ~0xC0); */
268}
269
270
271void via_init_afterscan(void)
272{
273    /* Modify IDE controller setup */
274    pci_write_cfg_byte(0, 7<<3|1, PCI_LATENCY_TIMER, 0x20);
275    pci_write_cfg_byte(0, 7<<3|1, PCI_COMMAND, PCI_COMMAND_IO|PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER);
276    pci_write_cfg_byte(0, 7<<3|1, PCI_INTERRUPT_LINE, 0xff);
277    pci_write_cfg_byte(0, 7<<3|1, 0x40, 0x0b);   /* FIXME: Might depend on drives connected */
278    pci_write_cfg_byte(0, 7<<3|1, 0x41, 0x42);   /* FIXME: Might depend on drives connected */
279    pci_write_cfg_byte(0, 7<<3|1, 0x43, 0x05);
280    pci_write_cfg_byte(0, 7<<3|1, 0x44, 0x18);
281    pci_write_cfg_byte(0, 7<<3|1, 0x45, 0x10);
282    pci_write_cfg_byte(0, 7<<3|1, 0x4e, 0x22);   /* FIXME: Not documented, but set in PC bios */
283    pci_write_cfg_byte(0, 7<<3|1, 0x4f, 0x20);   /* FIXME: Not documented */
284
285    /* Modify some values in the USB controller */
286    pci_write_cfg_byte(0, 7<<3|2, 0x05, 0x17);
287    pci_write_cfg_byte(0, 7<<3|2, 0x06, 0x01);
288    pci_write_cfg_byte(0, 7<<3|2, 0x41, 0x12);
289    pci_write_cfg_byte(0, 7<<3|2, 0x42, 0x03);
290    pci_write_cfg_byte(0, 7<<3|2, PCI_LATENCY_TIMER, 0x40);
291
292    pci_write_cfg_byte(0, 7<<3|3, 0x05, 0x17);
293    pci_write_cfg_byte(0, 7<<3|3, 0x06, 0x01);
294    pci_write_cfg_byte(0, 7<<3|3, 0x41, 0x12);
295    pci_write_cfg_byte(0, 7<<3|3, 0x42, 0x03);
296    pci_write_cfg_byte(0, 7<<3|3, PCI_LATENCY_TIMER, 0x40);
297
298
299}
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