source: SVN/rincon/u-boot/board/Marvell/common/memory.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

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Signed-off-by: Tim Harvey <tharvey@…>

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1/*
2 * Copyright - Galileo technology.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 *
25 * written or collected and sometimes rewritten by
26 * Ingo Assmus <ingo.assmus@keymile.com>
27 *
28 */
29
30
31#include <common.h>
32#include "../include/core.h"
33#include "../include/memory.h"
34
35/*******************************************************************************
36* memoryGetBankBaseAddress - Returns the base address of a memory bank.
37* DESCRIPTION:
38*       This function returns the base address of one of the SDRAM’s memory
39*       banks. There are 4 memory banks and each one represents one DIMM side.
40* INPUT:
41*       MEMORY_BANK bank - Selects one of the four banks as defined in Memory.h.
42* OUTPUT:
43*       None.
44* RETURN:
45*       32 bit Memory bank base address.
46*******************************************************************************/
47static unsigned long memoryGetBankRegOffset (MEMORY_BANK bank)
48{
49        switch (bank) {
50        case BANK0:
51                return SCS_0_LOW_DECODE_ADDRESS;
52        case BANK1:
53                return SCS_1_LOW_DECODE_ADDRESS;
54        case BANK2:
55                return SCS_2_LOW_DECODE_ADDRESS;
56        case BANK3:
57                return SCS_3_LOW_DECODE_ADDRESS;
58
59        }
60        return SCS_0_LOW_DECODE_ADDRESS;        /* default value */
61}
62
63unsigned int memoryGetBankBaseAddress (MEMORY_BANK bank)
64{
65        unsigned int base;
66        unsigned int regOffset = memoryGetBankRegOffset (bank);
67
68        GT_REG_READ (regOffset, &base);
69        base = base << 16;      /* MV6436x */
70        return base;
71}
72
73/*******************************************************************************
74* memoryGetDeviceBaseAddress - Returns the base address of a device.
75* DESCRIPTION:
76*       This function returns the base address of a device on the system. There
77*       are 5 possible devices (0 - 4 and one boot device) as defined in
78*       gtMemory.h. Each of the device parameters is maped to one of the CS
79*       (Devices chip selects) base address register.
80* INPUT:
81*       device - Selects one of the five devices as defined in Memory.h.
82* OUTPUT:
83*       None.
84* RETURN:
85*       32 bit Device base address.
86*
87*******************************************************************************/
88static unsigned int memoryGetDeviceRegOffset (DEVICE device)
89{
90        switch (device) {
91        case DEVICE0:
92                return CS_0_LOW_DECODE_ADDRESS;
93        case DEVICE1:
94                return CS_1_LOW_DECODE_ADDRESS;
95        case DEVICE2:
96                return CS_2_LOW_DECODE_ADDRESS;
97        case DEVICE3:
98                return CS_3_LOW_DECODE_ADDRESS;
99        case BOOT_DEVICE:
100                return BOOTCS_LOW_DECODE_ADDRESS;
101        }
102        return CS_0_LOW_DECODE_ADDRESS; /* default value */
103}
104
105unsigned int memoryGetDeviceBaseAddress (DEVICE device)
106{
107        unsigned int regBase;
108        unsigned int regOffset = memoryGetDeviceRegOffset (device);
109
110        GT_REG_READ (regOffset, &regBase);
111
112        regBase = regBase << 16;        /* MV6436x */
113        return regBase;
114}
115
116/*******************************************************************************
117* MemoryGetPciBaseAddr - Returns the base address of a PCI window.
118* DESCRIPTION:
119*       This function returns the base address of a PCI window. There are 5
120*       possible PCI windows (memory 0 - 3 and one for I/O) for each PCI
121*       interface as defined in gtMemory.h, used by the CPU's address decoding
122*       mechanism.
123*       New in MV6436x
124* INPUT:
125*       pciWindow - Selects one of the PCI windows as defined in Memory.h.
126* OUTPUT:
127*       None.
128* RETURN:
129*       32 bit PCI window base address.
130*******************************************************************************/
131unsigned int MemoryGetPciBaseAddr (PCI_MEM_WINDOW pciWindow)
132{
133        unsigned int baseAddrReg, base;
134
135        switch (pciWindow) {
136        case PCI_0_IO:
137                baseAddrReg = PCI_0I_O_LOW_DECODE_ADDRESS;      /*PCI_0_IO_BASE_ADDR;  */
138                break;
139        case PCI_0_MEM0:
140                baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS;  /*PCI_0_MEMORY0_BASE_ADDR; */
141                break;
142        case PCI_0_MEM1:
143                baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS;  /*PCI_0_MEMORY1_BASE_ADDR; */
144                break;
145        case PCI_0_MEM2:
146                baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS;  /*PCI_0_MEMORY2_BASE_ADDR;  */
147                break;
148        case PCI_0_MEM3:
149                baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS;  /*PCI_0_MEMORY3_BASE_ADDR;  */
150                break;
151#ifdef INCLUDE_PCI_1
152        case PCI_1_IO:
153                baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS;      /*PCI_1_IO_BASE_ADDR;  */
154                break;
155        case PCI_1_MEM0:
156                baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS;  /*PCI_1_MEMORY0_BASE_ADDR; */
157                break;
158        case PCI_1_MEM1:
159                baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS;  /*PCI_1_MEMORY1_BASE_ADDR;  */
160                break;
161        case PCI_1_MEM2:
162                baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS;  /*PCI_1_MEMORY2_BASE_ADDR;  */
163                break;
164        case PCI_1_MEM3:
165                baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS;  /*PCI_1_MEMORY3_BASE_ADDR; */
166                break;
167#endif /* INCLUDE_PCI_1 */
168        default:
169                return 0xffffffff;
170        }
171        GT_REG_READ (baseAddrReg, &base);
172        return (base << 16);
173}
174
175/*******************************************************************************
176* memoryGetBankSize - Returns the size of a memory bank.
177* DESCRIPTION:
178*       This function returns the size of memory bank as described in
179*       'gtMemoryGetBankBaseAddress' function.
180* INPUT:
181*       bank - Selects one of the four banks as defined in Memory.h.
182* OUTPUT:
183*       None.
184* RETURN:
185*       32 bit size memory bank size or 0 for a closed or non populated bank.
186*
187*******************************************************************************/
188unsigned int memoryGetBankSize (MEMORY_BANK bank)
189{
190        unsigned int sizeReg, size;
191        MEMORY_WINDOW window;
192
193        switch (bank) {
194        case BANK0:
195                sizeReg = SCS_0_HIGH_DECODE_ADDRESS;    /* CS_0_SIZE; */
196                window = CS_0_WINDOW;
197                break;
198        case BANK1:
199                sizeReg = SCS_1_HIGH_DECODE_ADDRESS;    /* CS_1_SIZE; */
200                window = CS_1_WINDOW;
201                break;
202        case BANK2:
203                sizeReg = SCS_2_HIGH_DECODE_ADDRESS;    /* CS_2_SIZE; */
204                window = CS_2_WINDOW;
205                break;
206        case BANK3:
207                sizeReg = SCS_3_HIGH_DECODE_ADDRESS;    /* CS_3_SIZE; */
208                window = CS_3_WINDOW;
209                break;
210        default:
211                return 0;
212                break;
213        }
214        /* If the window is closed, a size of 0 is returned */
215        if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED)
216                return 0;
217        GT_REG_READ (sizeReg, &size);
218        size = ((size << 16) | 0xffff) + 1;
219        return size;
220}
221
222/*******************************************************************************
223* memoryGetDeviceSize - Returns the size of a device memory space.
224* DESCRIPTION:
225*       This function returns the memory space size of a given device.
226* INPUT:
227*       device - Selects one of the five devices as defined in Memory.h.
228* OUTPUT:
229*       None.
230* RETURN:
231*       32 bit size of a device memory space.
232*******************************************************************************/
233unsigned int memoryGetDeviceSize (DEVICE device)
234{
235        unsigned int sizeReg, size;
236        MEMORY_WINDOW window;
237
238        switch (device) {
239        case DEVICE0:
240                sizeReg = CS_0_HIGH_DECODE_ADDRESS;     /*DEV_CS0_SIZE; */
241                window = DEVCS_0_WINDOW;
242                break;
243        case DEVICE1:
244                sizeReg = CS_1_HIGH_DECODE_ADDRESS;     /*DEV_CS1_SIZE; */
245                window = DEVCS_1_WINDOW;
246                break;
247        case DEVICE2:
248                sizeReg = CS_2_HIGH_DECODE_ADDRESS;     /*DEV_CS2_SIZE; */
249                window = DEVCS_2_WINDOW;
250                break;
251        case DEVICE3:
252                sizeReg = CS_3_HIGH_DECODE_ADDRESS;     /*DEV_CS3_SIZE; */
253                window = DEVCS_3_WINDOW;
254                break;
255        case BOOT_DEVICE:
256                sizeReg = BOOTCS_HIGH_DECODE_ADDRESS;   /*BOOTCS_SIZE; */
257                window = BOOT_CS_WINDOW;
258                break;
259        default:
260                return 0;
261                break;
262        }
263        /* If the window is closed, a size of 0 is returned */
264        if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED)
265                return 0;
266        GT_REG_READ (sizeReg, &size);
267        size = ((size << 16) | 0xffff) + 1;
268        return size;
269}
270
271/*******************************************************************************
272* MemoryGetPciWindowSize - Returns the size of a PCI memory window.
273* DESCRIPTION:
274*       This function returns the size of a PCI window.
275* INPUT:
276*       pciWindow - Selects one of the PCI memory windows as defined in
277*       Memory.h.
278* OUTPUT:
279*       None.
280* RETURN:
281*       32 bit size of a PCI memory window.
282*******************************************************************************/
283unsigned int MemoryGetPciWindowSize (PCI_MEM_WINDOW pciWindow)
284{
285        unsigned int sizeReg, size;
286
287        switch (pciWindow) {
288        case PCI_0_IO:
289                sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS; /*PCI_0_IO_SIZE; */
290                break;
291        case PCI_0_MEM0:
292                sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS;     /*PCI_0_MEMORY0_SIZE; */
293                break;
294        case PCI_0_MEM1:
295                sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS;     /*PCI_0_MEMORY1_SIZE; */
296                break;
297        case PCI_0_MEM2:
298                sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS;     /*PCI_0_MEMORY2_SIZE; */
299                break;
300        case PCI_0_MEM3:
301                sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS;     /*PCI_0_MEMORY3_SIZE; */
302                break;
303#ifdef INCLUDE_PCI_1
304        case PCI_1_IO:
305                sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS; /*PCI_1_IO_SIZE; */
306                break;
307        case PCI_1_MEM0:
308                sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS;     /*PCI_1_MEMORY0_SIZE; */
309                break;
310        case PCI_1_MEM1:
311                sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS;     /*PCI_1_MEMORY1_SIZE;  */
312                break;
313        case PCI_1_MEM2:
314                sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS;     /*PCI_1_MEMORY2_SIZE;  */
315                break;
316        case PCI_1_MEM3:
317                sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS;     /*PCI_1_MEMORY3_SIZE; */
318                break;
319#endif /* INCLUDE_PCI_1 */
320        default:
321                return 0x0;
322        }
323        /* If the memory window is disabled, retrun size = 0 */
324        if (MemoryGetMemWindowStatus (PCI_0_IO_WINDOW << pciWindow)
325            == MEM_WINDOW_DISABLED)
326                return 0;
327        GT_REG_READ (sizeReg, &size);
328        size = ((size << 16) | 0xffff) + 1;
329        return size;
330}
331
332/*******************************************************************************
333* memoryGetDeviceWidth - Returns the width of a given device.
334* DESCRIPTION:
335*       The MV's device interface supports up to 32 Bit wide devices. A device
336*       can have a  1, 2, 4 or 8 Bytes data width. This function returns the
337*       width of a device as defined by the user or the operating system.
338* INPUT:
339*       device - Selects one of the five devices as defined in Memory.h.
340* OUTPUT:
341*       None.
342* RETURN:
343*       Device width in Bytes (1,2,4 or 8), 0 if error had occurred.
344*******************************************************************************/
345unsigned int memoryGetDeviceWidth (DEVICE device)
346{
347        unsigned int width;
348        unsigned int regValue;
349
350        GT_REG_READ (DEVICE_BANK0PARAMETERS + device * 4, &regValue);
351        width = (regValue & (BIT20 | BIT21)) >> 20;
352        return (BIT0 << width);
353}
354
355/*******************************************************************************
356* memoryMapBank - Set new base address and size for one of the memory
357*                         banks.
358*
359* DESCRIPTION:
360*       The CPU interface address decoding map consists of 21 address windows
361*       for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
362*       window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
363*       space. Each address window is defined by two registers - base and size.
364*       The CPU address is compared with the values in the various CPU windows
365*       until a match is found and the address is than targeted to that window.
366*       This function sets new base and size for one the memory banks
367*       (CS0 - CS3). It is the programmer`s responsibility to make sure that
368*       there are no conflicts with other memory spaces. When two memory spaces
369*       overlap, the MV’s behavior is not defined .If a bank needs to be closed,
370*       set the ’bankLength’ parameter size to 0x0.
371*
372* INPUT:
373*       bank      - One of the memory banks (CS0-CS3) as defined in gtMemory.h.
374*       bankBase  - The memory bank base address.
375*       bankLength  - The memory bank size. This function will decrement the
376*                   'bankLength' parameter by one and then check if the size is
377*                   valid. A valid size must be programed from LSB to MSB as
378*                   sequence of ‘1’s followed by sequence of ‘0’s.
379*                   To close a memory window simply set the size to 0.
380*      NOTE!!!
381*       The size must be in 64Kbyte granularity.
382*       The base address must be aligned to the size.
383* OUTPUT:
384*       None.
385* RETURN:
386*       False for invalid size, true otherwise.
387*
388* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!!
389*
390*******************************************************************************/
391
392bool memoryMapBank (MEMORY_BANK bank, unsigned int bankBase,
393                    unsigned int bankLength)
394{
395        unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift;
396
397/*    PCI_INTERNAL_BAR pciBAR; */
398
399        switch (bank) {
400        case BANK0:
401                baseReg = SCS_0_LOW_DECODE_ADDRESS;     /*CS_0_BASE_ADDR; */
402                sizeReg = SCS_0_HIGH_DECODE_ADDRESS;    /*CS_0_SIZE; */
403/*        pciBAR = PCI_CS0_BAR; */
404                break;
405        case BANK1:
406                baseReg = SCS_1_LOW_DECODE_ADDRESS;     /*CS_1_BASE_ADDR; */
407                sizeReg = SCS_1_HIGH_DECODE_ADDRESS;    /*CS_1_SIZE; */
408                /*        pciBAR = SCS_0_HIGH_DECODE_ADDRESS; */ /*PCI_CS1_BAR; */
409                break;
410        case BANK2:
411                baseReg = SCS_2_LOW_DECODE_ADDRESS;     /*CS_2_BASE_ADDR; */
412                sizeReg = SCS_2_HIGH_DECODE_ADDRESS;    /*CS_2_SIZE; */
413/*        pciBAR = PCI_CS2_BAR;*/
414                break;
415        case BANK3:
416                baseReg = SCS_3_LOW_DECODE_ADDRESS;     /*CS_3_BASE_ADDR; */
417                sizeReg = SCS_3_HIGH_DECODE_ADDRESS;    /*CS_3_SIZE; */
418/*        pciBAR = PCI_CS3_BAR; */
419                break;
420        default:
421                return false;
422        }
423        /* If the size is 0, the window will be disabled */
424        if (bankLength == 0) {
425                MemoryDisableWindow (CS_0_WINDOW << bank);
426                /* Disable the BAR from the PCI slave side */
427/*        gtPci0DisableInternalBAR(pciBAR); */
428/*        gtPci1DisableInternalBAR(pciBAR); */
429                return true;
430        }
431        /* The base address must be aligned to the size */
432        if ((bankBase % bankLength) != 0) {
433                return false;
434        }
435        if (bankLength >= MINIMUM_MEM_BANK_SIZE) {
436                newBase = bankBase >> 16;
437                newSize = bankLength >> 16;
438                /* Checking that the size is a sequence of '1' followed by a
439                   sequence of '0' starting from LSB to MSB. */
440                temp = newSize - 1;
441                for (rShift = 0; rShift < 16; rShift++) {
442                        temp = temp >> rShift;
443                        if ((temp & 0x1) == 0) {        /* Either we got to the last '1' */
444                                                        /* or the size is not valid      */
445                                if (temp > 0x0)
446                                        return false;
447                                else
448                                        break;
449                        }
450                }
451#ifdef DEBUG
452                {
453                        unsigned int oldBase, oldSize;
454
455                        GT_REG_READ (baseReg, &oldBase);
456                        GT_REG_READ (sizeReg + 8, &oldSize);
457
458                        printf ("b%d Base:%x Size:%x -> Base:%x Size:%x\n",
459                                bank, oldBase, oldSize, newBase, newSize);
460                }
461#endif
462                /* writing the new values */
463                GT_REG_WRITE (baseReg, newBase);
464                GT_REG_WRITE (sizeReg, newSize - 1);
465                /* Enable back the window */
466                MemoryEnableWindow (CS_0_WINDOW << bank);
467                /* Enable the BAR from the PCI slave side */
468/*        gtPci0EnableInternalBAR(pciBAR); */
469/*        gtPci1EnableInternalBAR(pciBAR); */
470                return true;
471        }
472        return false;
473}
474
475
476/*******************************************************************************
477* memoryMapDeviceSpace - Set new base address and size for one of the device
478*                           windows.
479*
480* DESCRIPTION:
481*       The CPU interface address decoding map consists of 21 address windows
482*       for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
483*       window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
484*       space. Each address window is defined by two registers - base and size.
485*       The CPU address is compared with the values in the various CPU windows
486*       until a match is found and the address is than targeted to that window.
487*       This function sets new base and size for one the device windows
488*       (DEV_CS0 - DEV_CS3). It is the programmer`s responsibility to make sure
489*       that there are no conflicts with other memory spaces. When two memory
490*       spaces overlap, the MV’s behavior is not defined .If a device window
491*       needs to be closed, set the 'deviceLength' parameter size to 0x0.
492*
493* INPUT:
494*       device           - One of the device windows (DEV_CS0-DEV_CS3) as
495*                          defined in gtMemory.h.
496*       deviceBase - The device window base address.
497*       deviceLength - The device window size. This function will decrement
498*                          the 'deviceLength' parameter by one and then
499*                          check if the size is valid. A valid size must be
500*                          programed from LSB to MSB as sequence of ‘1’s
501*                          followed by sequence of ‘0’s.
502*                          To close a memory window simply set the size to 0.
503*
504*      NOTE!!!
505*       The size must be in 64Kbyte granularity.
506*       The base address must be aligned to the size.
507*
508* OUTPUT:
509*       None.
510*
511* RETURN:
512*       False for invalid size, true otherwise.
513*
514* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!!
515*
516*******************************************************************************/
517
518bool memoryMapDeviceSpace (DEVICE device, unsigned int deviceBase,
519                           unsigned int deviceLength)
520{
521        unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift;
522
523/*    PCI_INTERNAL_BAR pciBAR;*/
524
525        switch (device) {
526        case DEVICE0:
527                baseReg = CS_0_LOW_DECODE_ADDRESS;      /*DEV_CS0_BASE_ADDR; */
528                sizeReg = CS_0_HIGH_DECODE_ADDRESS;     /*DEV_CS0_SIZE; */
529/*        pciBAR = PCI_DEV_CS0_BAR; */
530                break;
531        case DEVICE1:
532                baseReg = CS_1_LOW_DECODE_ADDRESS;      /*DEV_CS1_BASE_ADDR; */
533                sizeReg = CS_1_HIGH_DECODE_ADDRESS;     /*DEV_CS1_SIZE; */
534/*        pciBAR = PCI_DEV_CS1_BAR; */
535                break;
536        case DEVICE2:
537                baseReg = CS_2_LOW_DECODE_ADDRESS;      /*DEV_CS2_BASE_ADDR; */
538                sizeReg = CS_2_HIGH_DECODE_ADDRESS;     /*DEV_CS2_SIZE; */
539/*        pciBAR = PCI_DEV_CS2_BAR; */
540                break;
541        case DEVICE3:
542                baseReg = CS_3_LOW_DECODE_ADDRESS;      /*DEV_CS3_BASE_ADDR; */
543                sizeReg = CS_3_HIGH_DECODE_ADDRESS;     /*DEV_CS3_SIZE; */
544/*        pciBAR = PCI_DEV_CS3_BAR; */
545                break;
546        case BOOT_DEVICE:
547                baseReg = BOOTCS_LOW_DECODE_ADDRESS;    /*BOOTCS_BASE_ADDR; */
548                sizeReg = BOOTCS_HIGH_DECODE_ADDRESS;   /*BOOTCS_SIZE; */
549/*        pciBAR = PCI_BOOT_CS_BAR; */
550                break;
551        default:
552                return false;
553        }
554        if (deviceLength == 0) {
555                MemoryDisableWindow (DEVCS_0_WINDOW << device);
556                /* Disable the BAR from the PCI slave side */
557/*        gtPci0DisableInternalBAR(pciBAR); */
558/*        gtPci1DisableInternalBAR(pciBAR); */
559                return true;
560        }
561        /* The base address must be aligned to the size */
562        if ((deviceBase % deviceLength) != 0) {
563                return false;
564        }
565        if (deviceLength >= MINIMUM_DEVICE_WINDOW_SIZE) {
566                newBase = deviceBase >> 16;
567                newSize = deviceLength >> 16;
568                /* Checking that the size is a sequence of '1' followed by a
569                   sequence of '0' starting from LSB to MSB. */
570                temp = newSize - 1;
571                for (rShift = 0; rShift < 16; rShift++) {
572                        temp = temp >> rShift;
573                        if ((temp & 0x1) == 0) {        /* Either we got to the last '1' */
574                                                        /* or the size is not valid       */
575                                if (temp > 0x0)
576                                        return false;
577                                else
578                                        break;
579                        }
580                }
581                /* writing the new values */
582                GT_REG_WRITE (baseReg, newBase);
583                GT_REG_WRITE (sizeReg, newSize - 1);
584                MemoryEnableWindow (DEVCS_0_WINDOW << device);
585                /* Enable the BAR from the PCI slave side */
586/*        gtPci0EnableInternalBAR(pciBAR); */
587/*        gtPci1EnableInternalBAR(pciBAR); */
588                return true;
589        }
590        return false;
591}
592
593/*******************************************************************************
594* MemorySetPciWindow - Set new base address and size for one of the PCI
595*                        windows.
596*
597* DESCRIPTION:
598*       The CPU interface address decoding map consists of 21 address windows
599*       for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
600*       window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
601*       space. Each address window is defined by two registers - base and size.
602*       The CPU address is compared with the values in the various CPU windows
603*       until a match is found and the address is than targeted to that window.
604*       This function sets new base and size for one the PCI windows
605*       (PCI memory0/1/2..). It is the programmer`s responsibility to make sure
606*       that there are no conflicts with other memory spaces. When two memory
607*       spaces overlap, the MV’s behavior is not defined .If a PCI window
608*       needs to be closed, set the 'pciWindowSize' parameter size to 0x0.
609*
610* INPUT:
611*       pciWindow     - One of the PCI windows as defined in gtMemory.h.
612*       pciWindowBase - The PCI window base address.
613*       pciWindowSize - The PCI window size. This function will decrement the
614*                       'pciWindowSize' parameter by one and then check if the
615*                       size is valid. A valid size must be programed from LSB
616*                       to MSB as sequence of ‘1’s followed by sequence of ‘0’s.
617*                       To close a memory window simply set the size to 0.
618*
619*      NOTE!!!
620*       The size must be in 64Kbyte granularity.
621*       The base address must be aligned to the size.
622*
623* OUTPUT:
624*       None.
625*
626* RETURN:
627*       False for invalid size, true otherwise.
628*
629*******************************************************************************/
630bool memorySetPciWindow (PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase,
631                         unsigned int pciWindowSize)
632{
633        unsigned int currentLow, baseAddrReg, sizeReg, temp, rShift;
634
635        switch (pciWindow) {
636        case PCI_0_IO:
637                baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS;      /*PCI_0_IO_BASE_ADDR; */
638                sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS; /*PCI_0_IO_SIZE; */
639                break;
640        case PCI_0_MEM0:
641                baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS;  /*PCI_0_MEMORY0_BASE_ADDR; */
642                sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS;     /*PCI_0_MEMORY0_SIZE; */
643                break;
644        case PCI_0_MEM1:
645                baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS;  /*PCI_0_MEMORY1_BASE_ADDR; */
646                sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS;     /*PCI_0_MEMORY1_SIZE; */
647                break;
648        case PCI_0_MEM2:
649                baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS;  /*PCI_0_MEMORY2_BASE_ADDR; */
650                sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS;     /*PCI_0_MEMORY2_SIZE; */
651                break;
652        case PCI_0_MEM3:
653                baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS;  /*PCI_0_MEMORY3_BASE_ADDR; */
654                sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS;     /*PCI_0_MEMORY3_SIZE; */
655                break;
656#ifdef INCLUDE_PCI_1
657        case PCI_1_IO:
658                baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS;      /*PCI_1_IO_BASE_ADDR; */
659                sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS; /*PCI_1_IO_SIZE; */
660                break;
661        case PCI_1_MEM0:
662                baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS;  /*PCI_1_MEMORY0_BASE_ADDR; */
663                sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS;     /*PCI_1_MEMORY0_SIZE; */
664                break;
665        case PCI_1_MEM1:
666                baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS;  /*PCI_1_MEMORY1_BASE_ADDR;  */
667                sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS;     /*PCI_1_MEMORY1_SIZE; */
668                break;
669        case PCI_1_MEM2:
670                baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS;  /*PCI_1_MEMORY2_BASE_ADDR;  */
671                sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS;     /*PCI_1_MEMORY2_SIZE; */
672                break;
673        case PCI_1_MEM3:
674                baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS;  /*PCI_1_MEMORY3_BASE_ADDR; */
675                sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS;     /*PCI_1_MEMORY3_SIZE; */
676                break;
677#endif /* INCLUDE_PCI_1 */
678        default:
679                return false;
680        }
681        if (pciWindowSize == 0) {
682                MemoryDisableWindow (PCI_0_IO_WINDOW << pciWindow);
683                return true;
684        }
685        /* The base address must be aligned to the size */
686        if ((pciWindowBase % pciWindowSize) != 0) {
687                return false;
688        }
689        if (pciWindowSize >= MINIMUM_PCI_WINDOW_SIZE) {
690                pciWindowBase >>= 16;
691                pciWindowSize >>= 16;
692                /* Checking that the size is a sequence of '1' followed by a
693                   sequence of '0' starting from LSB to MSB. */
694                temp = pciWindowSize - 1;
695                for (rShift = 0; rShift < 16; rShift++) {
696                        temp = temp >> rShift;
697                        if ((temp & 0x1) == 0) {        /* Either we got to the last '1' */
698                                                        /* or the size is not valid       */
699                                if (temp > 0x0)
700                                        return false;
701                                else
702                                        break;
703                        }
704                }
705                GT_REG_WRITE (sizeReg, pciWindowSize - 1);
706                GT_REG_READ (baseAddrReg, &currentLow);
707                pciWindowBase =
708                        (pciWindowBase & 0xfffff) | (currentLow & 0xfff00000);
709                GT_REG_WRITE (baseAddrReg, pciWindowBase);
710                MemoryEnableWindow (PCI_0_IO_WINDOW << pciWindow);
711                return true;
712        }
713        return false;
714}
715
716/*******************************************************************************
717* memoryMapInternalRegistersSpace - Sets new base address for the internal
718*                                  registers memory space.
719*
720* DESCRIPTION:
721*       This function set new base address for the internal register’s memory
722*       space (the size is fixed and cannot be modified). The function does not
723*       handle overlapping with other memory spaces, it is the programer's
724*       responsibility to ensure that overlapping does not occur.
725*       When two memory spaces overlap, the MV’s behavior is not defined.
726*
727* INPUT:
728*       internalRegBase - new base address for the internal register’s memory
729*                         space.
730*
731* OUTPUT:
732*       None.
733*
734* RETURN:
735*        true on success, false on failure
736*
737*******************************************************************************/
738/********************************************************************
739* memoryMapInternalRegistersSpace - Sets new base address for the internals
740*                                   registers.
741*
742* INPUTS:  unsigned int internalRegBase - The new base address.
743* RETURNS: true on success, false on failure
744*********************************************************************/
745bool memoryMapInternalRegistersSpace (unsigned int internalRegBase)
746{
747        unsigned int currentValue;
748        unsigned int internalValue = internalRegBase;
749
750        internalRegBase = (internalRegBase >> 16);
751        GT_REG_READ (INTERNAL_SPACE_DECODE, &currentValue);
752        internalRegBase = (currentValue & 0xff000000) | internalRegBase;
753        GT_REG_WRITE (INTERNAL_SPACE_DECODE, internalRegBase);
754        /* initializing also the global variable 'internalRegBaseAddr' */
755/*    gtInternalRegBaseAddr = internalValue; */
756        INTERNAL_REG_BASE_ADDR = internalValue;
757        return true;
758}
759
760/*******************************************************************************
761* memoryGetInternalRegistersSpace - Returns the internal registers Base
762*                                     address.
763*
764* DESCRIPTION:
765*       This function returns the base address of  the internal register’s
766*       memory space .
767*
768* INPUT:
769*       None.
770*
771* OUTPUT:
772*       None.
773*
774* RETURN:
775*       32 bit base address of the internal register’s memory space.
776*
777*******************************************************************************/
778unsigned int memoryGetInternalRegistersSpace (void)
779{
780        unsigned int currentValue = 0;
781
782        GT_REG_READ (INTERNAL_SPACE_DECODE, &currentValue);
783        return ((currentValue & 0x000fffff) << 16);
784}
785
786/*******************************************************************************
787* gtMemoryGetInternalSramBaseAddr - Returns the integrated SRAM base address.
788*
789* DESCRIPTION:
790*       The Atlantis incorporate integrated 2Mbit SRAM for general use. This
791*       funcnion return the SRAM's base address.
792* INPUT:
793*       None.
794* OUTPUT:
795*       None.
796* RETURN:
797*       32 bit SRAM's base address.
798*
799*******************************************************************************/
800unsigned int memoryGetInternalSramBaseAddr (void)
801{
802        return ((GTREGREAD (INTEGRATED_SRAM_BASE_ADDR) & 0xfffff) << 16);
803}
804
805/*******************************************************************************
806* gtMemorySetInternalSramBaseAddr - Set the integrated SRAM base address.
807*
808* DESCRIPTION:
809*       The Atlantis incorporate integrated 2Mbit SRAM for general use. This
810*       function sets a new base address to the SRAM .
811* INPUT:
812*       sramBaseAddress - The SRAM's base address.
813* OUTPUT:
814*       None.
815* RETURN:
816*       None.
817*
818*******************************************************************************/
819void gtMemorySetInternalSramBaseAddr (unsigned int sramBaseAddress)
820{
821        GT_REG_WRITE (INTEGRATED_SRAM_BASE_ADDR, sramBaseAddress >> 16);
822}
823
824/*******************************************************************************
825* memorySetProtectRegion - Set protection mode for one of the 8 regions.
826*
827* DESCRIPTION:
828*       The CPU interface supports configurable access protection. This includes
829*       up to eight address ranges defined to a different protection type :
830*       whether the address range is cacheable or not, whether it is writable or
831*       not , and whether it is accessible or not. A Low and High registers
832*       define each window while the minimum address range of each window is
833*       1Mbyte. An address driven by the CPU, in addition to the address
834*       decoding and remapping process, is compared against the eight Access
835*       Protection Low/High registers , if an address matches one of the windows
836*       , the MV device checks the transaction type against the protection bits
837*       defined in CPU Access Protection register, to determine if the access is
838*       allowed. This function set a protection mode to one of the 8 possible
839*       regions.
840*      NOTE:
841*       The CPU address windows are restricted to a size of  2 power n and the
842*       start address must be aligned to the window size. For example, if using
843*       a 16 MB window, the start address bits [23:0] must be 0.The MV's
844*       internal registers space is not protected, even if the access protection
845*       windows contain this space.
846*
847* INPUT:
848*       region - selects which region to be configured. The values defined in
849*                gtMemory.h:
850*
851*                 - MEM_REGION0
852*                 - MEM_REGION1
853*                 - etc.
854*
855*       memAccess - Allows or forbids access (read or write ) to the region. The
856*                   values defined in gtMemory.h:
857*
858*                    - MEM_ACCESS_ALLOWED
859*                    - MEM_ACCESS_FORBIDEN
860*
861*       memWrite - CPU write protection to the region. The values defined in
862*                  gtMemory.h:
863*
864*                   - MEM_WRITE_ALLOWED
865*                   - MEM_WRITE_FORBIDEN
866*
867*       cacheProtection - Defines whether caching the region is allowed or not.
868*                         The values defined in gtMemory.h:
869*
870*                          - MEM_CACHE_ALLOWED
871*                          - MEM_CACHE_FORBIDEN
872*
873*       baseAddress - the region's base Address.
874*       regionSize  - The region's size. This function will decrement the
875*                     'regionSize' parameter by one and then check if the size
876*                     is valid. A valid size must be programed from LSB to MSB
877*                     as sequence of ‘1’s followed by sequence of ‘0’s.
878*                     To close a memory window simply set the size to 0.
879*
880*      NOTE!!!
881*       The size must be in 64Kbyte granularity.
882*       The base address must be aligned to the size.
883*
884* OUTPUT:
885*       None.
886*
887* RETURN:
888*       False for invalid size, true otherwise.
889*
890*******************************************************************************/
891bool memorySetProtectRegion (MEMORY_PROTECT_WINDOW window,
892                             MEMORY_ACCESS memAccess,
893                             MEMORY_ACCESS_WRITE memWrite,
894                             MEMORY_CACHE_PROTECT cacheProtection,
895                             unsigned int baseAddress, unsigned int size)
896{
897        unsigned int dataForReg, temp, rShift;
898
899        if (size == 0) {
900                GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window),
901                              0x0);
902                return true;
903        }
904        /* The base address must be aligned to the size.  */
905        if (baseAddress % size != 0) {
906                return false;
907        }
908        if (size >= MINIMUM_ACCESS_WIN_SIZE) {
909                baseAddress = ((baseAddress >> 16) & 0xfffff);
910                dataForReg = baseAddress | ((memAccess << 20) & BIT20) |
911                        ((memWrite << 21) & BIT21) | ((cacheProtection << 22)
912                                                      & BIT22) | BIT31;
913                GT_REG_WRITE (CPU_PROTECT_WINDOW_0_BASE_ADDR + 0x10 * window,
914                              dataForReg);
915                size >>= 16;
916                /* Checking that the size is a sequence of '1' followed by a
917                   sequence of '0' starting from LSB to MSB. */
918                temp = size - 1;
919                for (rShift = 0; rShift < 16; rShift++) {
920                        temp = temp >> rShift;
921                        if ((temp & 0x1) == 0) {        /* Either we got to the last '1' */
922                                                        /* or the size is not valid       */
923                                if (temp > 0x0)
924                                        return false;
925                                else
926                                        break;
927                        }
928                }
929                GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window),
930                              size - 1);
931                return true;
932        }
933        return false;
934}
935
936/*******************************************************************************
937* gtMemoryDisableProtectRegion - Disable a protected window.
938*
939* DESCRIPTION:
940*       This function disable a protected window set by
941*       'gtMemorySetProtectRegion' function.
942*
943* INPUT:
944*       window - one of the 4 windows ( defined in gtMemory.h ).
945*
946* OUTPUT:
947*       None.
948*
949* RETURN:
950*       None.
951*
952*******************************************************************************/
953void memoryDisableProtectRegion (MEMORY_PROTECT_WINDOW window)
954{
955        RESET_REG_BITS (((CPU_PROTECT_WINDOW_0_BASE_ADDR) + (0x10 * window)),
956                        BIT31);
957}
958
959/*******************************************************************************
960* memorySetPciRemapValue - Set a remap value to a PCI memory space target.
961*
962* DESCRIPTION:
963*       In addition to the address decoding mechanism, the CPU has an address
964*       remapping mechanism to be used by every PCI decoding window. Each PCI
965*       window can be remaped to a desired address target according to the remap
966*       value within the remap register. The address remapping is useful when a
967*       CPU address range must be reallocated to a different location on the
968*       PCI bus. Also, it enables CPU access to a PCI agent located above the
969*       4Gbyte space. On system boot, each of the PCI memory spaces is maped to
970*       a defualt value (see CPU interface section in the MV spec for the
971*       default values). The remap mechanism does not always produce the desired
972*       address on the PCI bus because of the remap mechanism way of working
973*       (to fully understand why, please see the 'Address Remapping' section in
974*       the MV's spec). Therefor, this function sets a desired remap value to
975*       one of the PCI memory windows and return the effective address that
976*       should be used when exiting the PCI memory window. You should ALWAYS use
977*       the returned value by this function when remapping a PCI window and
978*       exiting it. If for example the base address of PCI0 memory 0 is
979*       0x90000000, the size is 0x03ffffff and the remap value is 0x11000000,
980*       the function will return the value of 0x91000000 that MUST
981*       be used to exit this memory window in order to achive the deisred
982*       remapping.
983*
984* INPUT:
985*       memoryWindow   - One of the PCI memory windows as defined in Memory.h
986*       remapValueLow  - The low remap value.
987*       remapValueHigh - The high remap value.
988* OUTPUT:
989*       None.
990*
991* RETURN:
992*       The effective base address to exit the PCI, or 0xffffffff if one of the
993*       parameters is erroneous or the effective base address is higher the top
994*       decode value.
995*
996*******************************************************************************/
997unsigned int memorySetPciRemapValue (PCI_MEM_WINDOW memoryWindow,
998                                     unsigned int remapValueHigh,
999                                     unsigned int remapValueLow)
1000{
1001        unsigned int pciMemWindowBaseAddrReg = 0, baseAddrValue = 0;
1002        unsigned int pciMemWindowSizeReg = 0, windowSizeValue = 0;
1003        unsigned int effectiveBaseAddress, remapRegLow, remapRegHigh;
1004
1005        /* Initializing the base and size variables of the PCI
1006           memory windows */
1007        switch (memoryWindow) {
1008        case PCI_0_IO:
1009                pciMemWindowBaseAddrReg = PCI_0_IO_BASE_ADDR;
1010                pciMemWindowSizeReg = PCI_0_IO_SIZE;
1011                remapRegLow = PCI_0_IO_ADDR_REMAP;
1012                remapRegHigh = PCI_0_IO_ADDR_REMAP;
1013                break;
1014        case PCI_0_MEM0:
1015                pciMemWindowBaseAddrReg = PCI_0_MEMORY0_BASE_ADDR;
1016                pciMemWindowSizeReg = PCI_0_MEMORY0_SIZE;
1017                remapRegLow = PCI_0_MEMORY0_LOW_ADDR_REMAP;
1018                remapRegHigh = PCI_0_MEMORY0_HIGH_ADDR_REMAP;
1019                break;
1020        case PCI_0_MEM1:
1021                pciMemWindowBaseAddrReg = PCI_0_MEMORY1_BASE_ADDR;
1022                pciMemWindowSizeReg = PCI_0_MEMORY1_SIZE;
1023                remapRegLow = PCI_0_MEMORY1_LOW_ADDR_REMAP;
1024                remapRegHigh = PCI_0_MEMORY1_HIGH_ADDR_REMAP;
1025                break;
1026        case PCI_0_MEM2:
1027                pciMemWindowBaseAddrReg = PCI_0_MEMORY2_BASE_ADDR;
1028                pciMemWindowSizeReg = PCI_0_MEMORY2_SIZE;
1029                remapRegLow = PCI_0_MEMORY2_LOW_ADDR_REMAP;
1030                remapRegHigh = PCI_0_MEMORY2_HIGH_ADDR_REMAP;
1031                break;
1032        case PCI_0_MEM3:
1033                pciMemWindowBaseAddrReg = PCI_0_MEMORY3_BASE_ADDR;
1034                pciMemWindowSizeReg = PCI_0_MEMORY3_SIZE;
1035                remapRegLow = PCI_0_MEMORY3_LOW_ADDR_REMAP;
1036                remapRegHigh = PCI_0_MEMORY3_HIGH_ADDR_REMAP;
1037                break;
1038#ifdef INCLUDE_PCI_1
1039        case PCI_1_IO:
1040                pciMemWindowBaseAddrReg = PCI_1_IO_BASE_ADDR;
1041                pciMemWindowSizeReg = PCI_1_IO_SIZE;
1042                remapRegLow = PCI_1_IO_ADDR_REMAP;
1043                remapRegHigh = PCI_1_IO_ADDR_REMAP;
1044                break;
1045        case PCI_1_MEM0:
1046                pciMemWindowBaseAddrReg = PCI_1_MEMORY0_BASE_ADDR;
1047                pciMemWindowSizeReg = PCI_1_MEMORY0_SIZE;
1048                remapRegLow = PCI_1_MEMORY0_LOW_ADDR_REMAP;
1049                remapRegHigh = PCI_1_MEMORY0_HIGH_ADDR_REMAP;
1050                break;
1051        case PCI_1_MEM1:
1052                pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR;
1053                pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE;
1054                remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP;
1055                remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP;
1056                break;
1057        case PCI_1_MEM2:
1058                pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR;
1059                pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE;
1060                remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP;
1061                remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP;
1062                break;
1063        case PCI_1_MEM3:
1064                pciMemWindowBaseAddrReg = PCI_1_MEMORY3_BASE_ADDR;
1065                pciMemWindowSizeReg = PCI_1_MEMORY3_SIZE;
1066                remapRegLow = PCI_1_MEMORY3_LOW_ADDR_REMAP;
1067                remapRegHigh = PCI_1_MEMORY3_HIGH_ADDR_REMAP;
1068                break;
1069#endif /* INCLUDE_PCI_1 */
1070        default:
1071                /* Retrun an invalid effective base address */
1072                return 0xffffffff;
1073        }
1074        /* Writing the remap value to the remap regisers */
1075        GT_REG_WRITE (remapRegHigh, remapValueHigh);
1076        GT_REG_WRITE (remapRegLow, remapValueLow >> 16);
1077        /* Reading the values from the base address and size registers */
1078        baseAddrValue = GTREGREAD (pciMemWindowBaseAddrReg) & 0xfffff;
1079        windowSizeValue = GTREGREAD (pciMemWindowSizeReg) & 0xffff;
1080        /* Start calculating the effective Base Address */
1081        effectiveBaseAddress = baseAddrValue << 16;
1082        /* The effective base address will be combined from the chopped (if any)
1083           remap value (according to the size value and remap mechanism) and the
1084           window's base address */
1085        effectiveBaseAddress |=
1086                (((windowSizeValue << 16) | 0xffff) & remapValueLow);
1087        /* If the effectiveBaseAddress exceed the window boundaries return an
1088           invalid value. */
1089        if (effectiveBaseAddress >
1090            ((baseAddrValue << 16) + ((windowSizeValue << 16) | 0xffff)))
1091                return 0xffffffff;
1092        return effectiveBaseAddress;
1093}
1094
1095/********************************************************************
1096* memorySetRegionSnoopMode - This function modifys one of the 4 regions which
1097*                            supports Cache Coherency.
1098*
1099*
1100* Inputs: SNOOP_REGION region - One of the four regions.
1101*         SNOOP_TYPE snoopType - There is four optional Types:
1102*                               1. No Snoop.
1103*                               2. Snoop to WT region.
1104*                               3. Snoop to WB region.
1105*                               4. Snoop & Invalidate to WB region.
1106*         unsigned int baseAddress - Base Address of this region.
1107*         unsigned int topAddress - Top Address of this region.
1108* Returns: false if one of the parameters is wrong and true else
1109*********************************************************************/
1110/* evb6260 code */
1111#if 0
1112bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
1113                              MEMORY_SNOOP_TYPE snoopType,
1114                              unsigned int baseAddress,
1115                              unsigned int regionLength)
1116{
1117    unsigned int snoopXbaseAddress;
1118    unsigned int snoopXtopAddress;
1119    unsigned int data;
1120    unsigned int snoopHigh = baseAddress + regionLength;
1121
1122    if( (region > MEM_SNOOP_REGION3) || (snoopType > MEM_SNOOP_WB) )
1123        return false;
1124    snoopXbaseAddress = SNOOP_BASE_ADDRESS_0 + 0x10 * region;
1125    snoopXtopAddress = SNOOP_TOP_ADDRESS_0 + 0x10 * region;
1126                                 if(regionLength == 0) /* closing the region */
1127    {
1128        GT_REG_WRITE(snoopXbaseAddress,0x0000ffff);
1129        GT_REG_WRITE(snoopXtopAddress,0);
1130        return true;
1131    }
1132    baseAddress = baseAddress & 0xffff0000;
1133    data = (baseAddress >> 16) | snoopType << 16;
1134    GT_REG_WRITE(snoopXbaseAddress,data);
1135    snoopHigh = (snoopHigh & 0xfff00000) >> 20;
1136    GT_REG_WRITE(snoopXtopAddress,snoopHigh - 1);
1137    return true;
1138}
1139#endif
1140
1141/********************************************************************
1142* memoryRemapAddress - This fubction used for address remapping.
1143*
1144*
1145* Inputs: regOffset: remap register
1146*         remapValue :
1147* Returns: false if one of the parameters is erroneous,true otherwise.
1148*
1149* Not needed function To_do !!!!
1150*********************************************************************/
1151bool memoryRemapAddress (unsigned int remapReg, unsigned int remapValue)
1152{
1153        unsigned int valueForReg;
1154
1155        valueForReg = (remapValue & 0xfff00000) >> 20;
1156        GT_REG_WRITE (remapReg, valueForReg);
1157        return true;
1158}
1159
1160/*******************************************************************************
1161* memoryGetDeviceParam - Extract the device parameters from the device bank
1162*                          parameters register.
1163*
1164* DESCRIPTION:
1165*       To allow interfacing with very slow devices and fast synchronous SRAMs,
1166*       each device can be programed to different timing parameters. Each bank
1167*       has its own parameters register. Bank width can be programmed to 8, 16,
1168*       or 32-bits. Bank timing parameters can be programmed to support
1169*       different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O
1170*       Controllers). The MV allows you to set timing parameters and width for
1171*       each device through parameters register .
1172*       This function extracts the parameters described from the Device Bank
1173*       parameters register and fills the given 'deviceParam' (defined in
1174*       gtMemory.h) structure with the read data.
1175*
1176* INPUT:
1177*       deviceParam -  pointer to a structure DEVICE_PARAM (defined in
1178*                      Memory.h).For details about each structure field please
1179*                      see the device timing parameter section in the MV
1180*                      datasheet.
1181*       deviceNum  -   Select on of the five device banks (defined in
1182*                      Memory.h) :
1183*
1184*                       - DEVICE0
1185*                       - DEVICE1
1186*                       - DEVICE2
1187*                       - etc.
1188*
1189* OUTPUT:
1190*       None.
1191*
1192* RETURN:
1193*       false if one of the parameters is erroneous,true otherwise.
1194*
1195*******************************************************************************/
1196/********************************************************************
1197* memoryGetDeviceParam - This function used for getting device parameters from
1198*                        DEVICE BANK PARAMETERS REGISTER
1199*
1200*
1201* Inputs:        - deviceParam: STRUCT with paramiters for DEVICE BANK
1202*                  PARAMETERS REGISTER
1203*                - deviceNum : number of device
1204* Returns: false if one of the parameters is erroneous,true otherwise.
1205*********************************************************************/
1206
1207bool memoryGetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum)
1208{
1209        unsigned int valueOfReg;
1210        unsigned int calcData;
1211
1212        if (deviceNum > 4)
1213                return false;
1214        GT_REG_READ (DEVICE_BANK0PARAMETERS + 4 * deviceNum, &valueOfReg);
1215        calcData = (0x7 & valueOfReg) + ((BIT22 & valueOfReg) >> 19);
1216        deviceParam->turnOff = calcData;        /* Turn Off */
1217
1218        calcData = ((0x78 & valueOfReg) >> 3) + ((BIT23 & valueOfReg) >> 19);
1219        deviceParam->acc2First = calcData;      /* Access To First */
1220
1221        calcData = ((0x780 & valueOfReg) >> 7) + ((BIT24 & valueOfReg) >> 20);
1222        deviceParam->acc2Next = calcData;       /* Access To Next */
1223
1224        calcData =
1225                ((0x3800 & valueOfReg) >> 11) + ((BIT25 & valueOfReg) >> 22);
1226        deviceParam->ale2Wr = calcData; /* Ale To Write */
1227
1228        calcData = ((0x1c000 & valueOfReg) >> 14) +
1229                ((BIT26 & valueOfReg) >> 23);
1230        deviceParam->wrLow = calcData;  /* Write Active */
1231
1232        calcData = ((0xe0000 & valueOfReg) >> 17) +
1233                ((BIT27 & valueOfReg) >> 24);
1234        deviceParam->wrHigh = calcData; /* Write High */
1235
1236        calcData = ((0x300000 & valueOfReg) >> 20);
1237        deviceParam->deviceWidth = (BIT0 << calcData);  /* In bytes */
1238        calcData = ((0x30000000 & valueOfReg) >> 28);
1239        deviceParam->badrSkew = calcData;       /* Cycles gap between BAdr
1240                                                   toggle to read data sample. */
1241        calcData = ((0x40000000 & valueOfReg) >> 30);
1242        deviceParam->DPEn = calcData;   /*  Data Parity enable  */
1243        return true;
1244}
1245
1246/*******************************************************************************
1247* memorySetDeviceParam - Set new parameters for a device.
1248*
1249*
1250* DESCRIPTION:
1251*       To allow interfacing with very slow devices and fast synchronous SRAMs,
1252*       each device can be programed to different timing parameters. Each bank
1253*       has its own parameters register. Bank width can be programmed to 8, 16,
1254*       or 32-bits. Bank timing parameters can be programmed to support
1255*       different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O
1256*       Controllers). The MV allows you to set timing parameters and width for
1257*       each device through parameters register. This function set new
1258*       parameters to a device Bank from the delivered structure 'deviceParam'
1259*       (defined in gtMemory.h). The structure must be initialized with data
1260*       prior to the use of these function.
1261*
1262* INPUT:
1263*       deviceParam -  pointer to a structure DEVICE_PARAM (defined in
1264*                      Memory.h).For details about each structure field please
1265*                      see the device timing parameter section in the MV
1266*                      datasheet.
1267*       deviceNum  -   Select on of the five device banks (defined in
1268*                      Memory.h) :
1269*
1270*                       - DEVICE0
1271*                       - DEVICE1
1272*                       - DEVICE2
1273*                       - etc.
1274*
1275* OUTPUT:
1276*       None.
1277*
1278* RETURN:
1279*       false if one of the parameters is erroneous,true otherwise.
1280*
1281*******************************************************************************/
1282/********************************************************************
1283* memorySetDeviceParam - This function used for setting device parameters to
1284*                        DEVICE BANK PARAMETERS REGISTER
1285*
1286*
1287* Inputs:        - deviceParam: STRUCT for store paramiters from DEVICE BANK
1288*                  PARAMETERS REGISTER
1289*                - deviceNum : number of device
1290* Returns: false if one of the parameters is erroneous,true otherwise.
1291*********************************************************************/
1292bool memorySetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum)
1293{
1294        unsigned int valueForReg;
1295
1296        if ((deviceParam->turnOff > 0x7) || (deviceParam->acc2First > 0xf) ||
1297            (deviceParam->acc2Next > 0xf) || (deviceParam->ale2Wr > 0x7) ||
1298            (deviceParam->wrLow > 0x7) || (deviceParam->wrHigh > 0x7) ||
1299            (deviceParam->badrSkew > 0x2) || (deviceParam->DPEn > 0x1)) {
1300                return false;
1301        }
1302        valueForReg = (((deviceParam->turnOff) & 0x7) |
1303                       (((deviceParam->turnOff) & 0x8) << 19) |
1304                       (((deviceParam->acc2First) & 0xf) << 3) |
1305                       (((deviceParam->acc2First) & 0x10) << 19) |
1306                       (((deviceParam->acc2Next) & 0xf) << 7) |
1307                       (((deviceParam->acc2Next) & 0x10) << 20) |
1308                       (((deviceParam->ale2Wr) & 0x7) << 11) |
1309                       (((deviceParam->ale2Wr) & 0xf) << 22) |
1310                       (((deviceParam->wrLow) & 0x7) << 14) |
1311                       (((deviceParam->wrLow) & 0xf) << 23) |
1312                       (((deviceParam->wrHigh) & 0x7) << 17) |
1313                       (((deviceParam->wrHigh) & 0xf) << 24) |
1314                       (((deviceParam->badrSkew) & 0x3) << 28) |
1315                       (((deviceParam->DPEn) & 0x1) << 30));
1316
1317        /* insert the device width: */
1318        switch (deviceParam->deviceWidth) {
1319        case 1:
1320                valueForReg = valueForReg | _8BIT;
1321                break;
1322        case 2:
1323                valueForReg = valueForReg | _16BIT;
1324                break;
1325        case 4:
1326                valueForReg = valueForReg | _32BIT;
1327                break;
1328        default:
1329                valueForReg = valueForReg | _8BIT;
1330                break;
1331        }
1332        GT_REG_WRITE (DEVICE_BANK0PARAMETERS + 4 * deviceNum, valueForReg);
1333        return true;
1334}
1335
1336/*******************************************************************************
1337* MemoryDisableWindow - Disable a memory space by the disable bit.
1338* DESCRIPTION:
1339*       This function disables one of the 21 availiable windows dedicated for
1340*       the CPU decoding mechanism. Its possible to combine several windows with
1341*       the OR command.
1342* INPUT:
1343*       window - One or more of the memory windows (defined in gtMemory.h).
1344* OUTPUT:
1345*       None.
1346* RETURN:
1347*       None.
1348*******************************************************************************/
1349void MemoryDisableWindow (MEMORY_WINDOW window)
1350{
1351        SET_REG_BITS (BASE_ADDR_ENABLE, window);
1352}
1353
1354/*******************************************************************************
1355* MemoryEnableWindow - Enable a memory space that was disabled by
1356*                       'MemoryDisableWindow'.
1357* DESCRIPTION:
1358*       This function enables one of the 21 availiable windows dedicated for the
1359*       CPU decoding mechanism. Its possible to combine several windows with the
1360*       OR command.
1361* INPUT:
1362*       window - One or more of the memory windows (defined in gtMemory.h).
1363* OUTPUT:
1364*       None.
1365* RETURN:
1366*       None.
1367*******************************************************************************/
1368void MemoryEnableWindow (MEMORY_WINDOW window)
1369{
1370        RESET_REG_BITS (BASE_ADDR_ENABLE, window);
1371}
1372
1373/*******************************************************************************
1374* MemoryGetMemWindowStatus - This function check whether the memory window is
1375*                              disabled or not.
1376* DESCRIPTION:
1377*       This function checks if the given memory window is closed .
1378* INPUT:
1379*       window - One or more of the memory windows (defined in gtMemory.h).
1380* OUTPUT:
1381*       None.
1382* RETURN:
1383*       True for a closed window, false otherwise .
1384*******************************************************************************/
1385MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus (MEMORY_WINDOW window)
1386{
1387        if (GTREGREAD (BASE_ADDR_ENABLE) & window)
1388                return MEM_WINDOW_DISABLED;
1389        return MEM_WINDOW_ENABLED;
1390}
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