source: SVN/rincon/u-boot/board/Marvell/include/core.h @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

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Signed-off-by: Tim Harvey <tharvey@…>

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1/* Core.h - Basic core logic functions and definitions */
2
3/* Copyright Galileo Technology. */
4
5/*
6DESCRIPTION
7This header file contains simple read/write macros for addressing
8the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address
9space). The macros take care of Big/Little endian conversions.
10*/
11
12#ifndef __INCcoreh
13#define __INCcoreh
14
15#include "mv_gen_reg.h"
16
17extern unsigned int INTERNAL_REG_BASE_ADDR;
18
19/****************************************/
20/*          GENERAL Definitions                 */
21/****************************************/
22
23#define NO_BIT          0x00000000
24#define BIT0            0x00000001
25#define BIT1            0x00000002
26#define BIT2            0x00000004
27#define BIT3            0x00000008
28#define BIT4            0x00000010
29#define BIT5            0x00000020
30#define BIT6            0x00000040
31#define BIT7            0x00000080
32#define BIT8            0x00000100
33#define BIT9            0x00000200
34#define BIT10           0x00000400
35#define BIT11           0x00000800
36#define BIT12           0x00001000
37#define BIT13           0x00002000
38#define BIT14           0x00004000
39#define BIT15           0x00008000
40#define BIT16           0x00010000
41#define BIT17           0x00020000
42#define BIT18           0x00040000
43#define BIT19           0x00080000
44#define BIT20           0x00100000
45#define BIT21           0x00200000
46#define BIT22           0x00400000
47#define BIT23           0x00800000
48#define BIT24           0x01000000
49#define BIT25           0x02000000
50#define BIT26           0x04000000
51#define BIT27           0x08000000
52#define BIT28           0x10000000
53#define BIT29           0x20000000
54#define BIT30           0x40000000
55#define BIT31           0x80000000
56
57#define _1K             0x00000400
58#define _2K             0x00000800
59#define _4K             0x00001000
60#define _8K             0x00002000
61#define _16K            0x00004000
62#define _32K            0x00008000
63#define _64K            0x00010000
64#define _128K           0x00020000
65#define _256K           0x00040000
66#define _512K           0x00080000
67
68#define _1M             0x00100000
69#define _2M             0x00200000
70#define _3M             0x00300000
71#define _4M             0x00400000
72#define _5M             0x00500000
73#define _6M             0x00600000
74#define _7M             0x00700000
75#define _8M             0x00800000
76#define _9M             0x00900000
77#define _10M            0x00a00000
78#define _11M            0x00b00000
79#define _12M            0x00c00000
80#define _13M            0x00d00000
81#define _14M            0x00e00000
82#define _15M            0x00f00000
83#define _16M            0x01000000
84
85#define _32M            0x02000000
86#define _64M            0x04000000
87#define _128M           0x08000000
88#define _256M           0x10000000
89#define _512M           0x20000000
90
91#define _1G             0x40000000
92#define _2G             0x80000000
93
94#ifndef BOOL_WAS_DEFINED
95#define BOOL_WAS_DEFINED
96typedef enum _bool{false,true} bool;
97#endif
98
99/* Little to Big endian conversion macros */
100
101#ifdef LE /* Little Endian */
102#define SHORT_SWAP(X) (X)
103#define WORD_SWAP(X) (X)
104#define LONG_SWAP(X) ((l64)(X))
105
106#else    /* Big Endian */
107#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8))
108
109#define WORD_SWAP(X) (((X)&0xff)<<24)+      \
110                    (((X)&0xff00)<<8)+      \
111                    (((X)&0xff0000)>>8)+    \
112                    (((X)&0xff000000)>>24)
113
114#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+               \
115                            (((X)&0xff00ULL)<<40)+              \
116                            (((X)&0xff0000ULL)<<24)+            \
117                            (((X)&0xff000000ULL)<<8)+           \
118                            (((X)&0xff00000000ULL)>>8)+         \
119                            (((X)&0xff0000000000ULL)>>24)+      \
120                            (((X)&0xff000000000000ULL)>>40)+    \
121                            (((X)&0xff00000000000000ULL)>>56))
122
123#endif
124
125#ifndef NULL
126#define NULL 0
127#endif
128
129/* Those two definitions were defined to be compatible with MIPS */
130#define NONE_CACHEABLE          0x00000000
131#define CACHEABLE                       0x00000000
132
133/* 750 cache line */
134#define CACHE_LINE_SIZE 32
135#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1)
136#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS)
137
138/* Read/Write to/from GT`s internal registers */
139#define GT_REG_READ(offset, pData)                                          \
140*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE |                     \
141                INTERNAL_REG_BASE_ADDR | (offset))) ) ;                                              \
142*pData = WORD_SWAP(*pData)
143
144#define GTREGREAD(offset)                                                   \
145         (WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE |            \
146                   INTERNAL_REG_BASE_ADDR | (offset))) ))
147
148#define GT_REG_WRITE(offset, data)                                          \
149*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) =                   \
150                    WORD_SWAP(data)
151
152/* Write 32/16/8 bit */
153#define WRITE_CHAR(address, data)                                           \
154        *((unsigned char *)(address)) = data
155#define WRITE_SHORT(address, data)                                          \
156        *((unsigned short *)(address)) = data
157#define WRITE_WORD(address, data)                                           \
158        *((unsigned int *)(address)) = data
159
160#define GT_WRITE_CHAR(address, data)     WRITE_CHAR(address, data)
161
162/* Write 32/16/8 bit NonCacheable */
163/*
164#define GT_WRITE_CHAR(address, data)                                           \
165        (*((unsigned char *)NONE_CACHEABLE(address))) = data
166#define GT_WRITE_SHORT(address, data)                                          \
167        (*((unsigned short *)NONE_CACHEABLE(address))) = data
168#define GT_WRITE_WORD(address, data)                                           \
169        (*((unsigned int *)NONE_CACHEABLE(address))) = data
170*/
171 /*#define GT_WRITE_CHAR(address, data)   ((*((volatile unsigned char *)NONE_CACHEABLE((address)))) = ((unsigned char)(data)))1 */
172
173 /*#define GT_WRITE_SHORT(address, data)   ((*((volatile unsigned short *)NONE_CACHEABLE((address)))) = ((unsigned short)(data)))1 */
174
175 /*#define GT_WRITE_WORD(address, data)  ((*((volatile unsigned int *)NONE_CACHEABLE((address)))) = ((unsigned int)(data)))1 */
176
177
178/* Read 32/16/8 bits - returns data in variable. */
179#define READ_CHAR(address, pData)                                           \
180        *pData = *((volatile unsigned char *)(address))
181
182#define READ_SHORT(address, pData)                                          \
183        *pData = *((volatile unsigned short *)(address))
184
185#define READ_WORD(address, pData)                                           \
186        *pData = *((volatile unsigned int *)(address))
187
188/* Read 32/16/8 bit - returns data direct. */
189#define READCHAR(address)                                                   \
190        *((volatile unsigned char *)((address) | NONE_CACHEABLE))
191
192#define READSHORT(address)                                                  \
193        *((volatile unsigned short *)((address) | NONE_CACHEABLE))
194
195#define READWORD(address)                                                   \
196        *((volatile unsigned int *)((address) | NONE_CACHEABLE))
197
198/* Those two Macros were defined to be compatible with MIPS */
199#define VIRTUAL_TO_PHY(x)    (((unsigned int)x) & 0xffffffff)
200#define PHY_TO_VIRTUAL(x)    (((unsigned int)x) | NONE_CACHEABLE)
201
202/*  SET_REG_BITS(regOffset,bits) -
203   gets register offset and bits: a 32bit value. It set to logic '1' in the
204   internal register the bits which given as an input example:
205   SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
206   '1' in register 0x840 while the other bits stays as is. */
207#define SET_REG_BITS(regOffset,bits) \
208        *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR |  \
209        regOffset) |= (unsigned int)WORD_SWAP(bits)
210
211/*  RESET_REG_BITS(regOffset,bits) -
212   gets register offset and bits: a 32bit value. It set to logic '0' in the
213   internal register the bits which given as an input example:
214   RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
215   '0' in register 0x840 while the other bits stays as is. */
216#define RESET_REG_BITS(regOffset,bits) \
217        *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR   \
218        | regOffset) &= ~( (unsigned int)WORD_SWAP(bits) )
219/* gets register offset and bits: a 32bit value. It set to logic '1' in the
220   internal register the bits which given as an input example:
221   GT_SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
222   '1' in register 0x840 while the other bits stays as is. */
223 /*#define GT_SET_REG_BITS(regOffset,bits)      ((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) | (regOffset)))) |= ((unsigned int)WORD_SWAP(bits)))1 */
224 /*#define GT_SET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits)1 */
225#define GT_SET_REG_BITS(regOffset,bits) SET_REG_BITS(regOffset,bits)
226/* gets register offset and bits: a 32bit value. It set to logic '0' in the
227   internal register the bits which given as an input example:
228   GT_RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to
229   logic '0' in register 0x840 while the other bits stays as is. */
230 /*#define GT_RESET_REG_BITS(regOffset,bits)    ((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) |  (regOffset)))) &= ~((unsigned int)WORD_SWAP(bits)))1 */
231#define GT_RESET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits)
232
233
234#define DEBUG_LED0_ON()        WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x8000,0)
235#define DEBUG_LED1_ON()        WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0xc000,0)
236#define DEBUG_LED2_ON()        WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x10000,0)
237#define DEBUG_LED0_OFF()      WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x14000,0)
238#define DEBUG_LED1_OFF()      WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x18000,0)
239#define DEBUG_LED2_OFF()      WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x1c000,0)
240
241#endif /* __INCcoreh */
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