source: SVN/rincon/u-boot/board/RPXlite_dw/RPXlite_dw.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 4.6 KB
Line 
1/*
2 * (C) Copyright 2004
3 * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Sam Song
26 * U-Boot port on RPXlite DW board : RPXlite_DW or LITE_DW
27 * Tested on working at 64MHz(CPU)/32MHz(BUS),48MHz/24MHz
28 * with 64MB, 2 SDRAM Micron chips,MT48LC16M16A2-75.
29 */
30
31#include <common.h>
32#include <mpc8xx.h>
33
34/* ------------------------------------------------------------------------- */
35static long int dram_size (long int, long int *, long int);
36/* ------------------------------------------------------------------------- */
37
38#define _NOT_USED_      0xFFFFCC25
39
40const uint sdram_table[] =
41{
42        /*
43         * Single Read. (Offset 00h in UPMA RAM)
44         */
45        0x0F03CC04, 0x00ACCC24, 0x1FF74C20, /* last */
46        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
47        _NOT_USED_,
48
49        /*
50         * Burst Read. (Offset 08h in UPMA RAM)
51         */
52        0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
53        0x01FFCC20, 0x1FF74C20, /* last */
54        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
55        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
56        _NOT_USED_, _NOT_USED_,
57
58        /*
59         * Single Write. (Offset 18h in UPMA RAM)
60         */
61        0x0F03CC02, 0x00AC0C24, 0x1FF74C25, /* last */
62        _NOT_USED_, _NOT_USED_, 0x0FA00C34,0x0FFFCC35,
63        _NOT_USED_,
64
65        /*
66         * Burst Write. (Offset 20h in UPMA RAM)
67         */
68        0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
69        0x01FFFC24, 0x1FF74C25, /* last */
70        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
71        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
72        _NOT_USED_, _NOT_USED_,
73
74        /*
75         * Refresh. (Offset 30h in UPMA RAM)
76         */
77        0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
78        _NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
79        0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, 0x0FFFCCB4,
80        /* INIT sequence RAM WORDS
81         * SDRAM Initialization (offset 0x36 in UPMA RAM)
82         * The above definition uses the remaining space
83         * to establish an initialization sequence,
84         * which is executed by a RUN command.
85         * The sequence is COMMAND INHIBIT(NOP),Precharge,
86         * Load Mode Register,NOP,Auto Refresh.
87         */
88
89        /*
90         * Exception. (Offset 3Ch in UPMA RAM)
91         */
92        0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
93};
94
95/*
96 * Check Board Identity:
97 */
98
99int checkboard (void)
100{
101        puts ("Board: RPXlite_DW\n") ;
102        return (0) ;
103}
104
105/* ------------------------------------------------------------------------- */
106
107phys_size_t initdram (int board_type)
108{
109        volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
110        volatile memctl8xx_t *memctl = &immap->im_memctl;
111        long int size9;
112
113        upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
114
115        /* Refresh clock prescalar */
116        memctl->memc_mptpr = CFG_MPTPR ;
117
118        memctl->memc_mar  = 0x00000088;
119
120        /* Map controller banks 1 to the SDRAM bank */
121        memctl->memc_or1 = CFG_OR1_PRELIM;
122        memctl->memc_br1 = CFG_BR1_PRELIM;
123
124        memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
125        /*Disable Periodic timer A. */
126
127        udelay(200);
128
129        /* perform SDRAM initializsation sequence */
130
131        memctl->memc_mcr  = 0x80002236; /* SDRAM bank 0 - refresh twice */
132
133        udelay(1);
134
135        memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
136
137        /*Enable Periodic timer A */
138
139        udelay (1000);
140
141         /* Check Bank 0 Memory Size
142          * try 9 column mode
143          */
144
145        size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
146
147        /*
148         * Final mapping:
149         */
150
151        memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
152
153        udelay (1000);
154
155        return (size9);
156}
157
158void rpxlite_init (void)
159{
160        /* Enable NVRAM */
161        *((uchar *) BCSR0) |= BCSR0_ENNVRAM;
162}
163
164/*
165 * Check memory range for valid RAM. A simple memory test determines
166 * the actually available RAM size between addresses `base' and
167 * `base + maxsize'. Some (not all) hardware errors are detected:
168 * - short between address lines
169 * - short between data lines
170 */
171static long int dram_size (long int mamr_value, long int *base,
172                           long int maxsize)
173{
174        volatile immap_t *immap = (immap_t *) CFG_IMMR;
175        volatile memctl8xx_t *memctl = &immap->im_memctl;
176
177        memctl->memc_mamr = mamr_value;
178
179        return (get_ram_size (base, maxsize));
180}
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