source: SVN/rincon/u-boot/board/RRvision/RRvision.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 2 years ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 6.0 KB
Line 
1/*
2 * (C) Copyright 2001-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <mpc8xx.h>
26
27/* ------------------------------------------------------------------------- */
28
29static long int dram_size (long int, long int *, long int);
30
31/* ------------------------------------------------------------------------- */
32
33#define _NOT_USED_      0xFFFFFFFF
34
35const uint sdram_table[] =
36{
37        /*
38         * Single Read. (Offset 0 in UPMA RAM)
39         */
40        0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
41        0x1FF77C47, /* last */
42        /*
43         * SDRAM Initialization (offset 5 in UPMA RAM)
44         *
45         * This is no UPM entry point. The following definition uses
46         * the remaining space to establish an initialization
47         * sequence, which is executed by a RUN command.
48         *
49         */
50                    0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
51        /*
52         * Burst Read. (Offset 8 in UPMA RAM)
53         */
54        0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
55        0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
56        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
57        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
58        /*
59         * Single Write. (Offset 18 in UPMA RAM)
60         */
61        0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
62        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
63        /*
64         * Burst Write. (Offset 20 in UPMA RAM)
65         */
66        0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
67        0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
68                                            _NOT_USED_,
69        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
70        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
71        /*
72         * Refresh  (Offset 30 in UPMA RAM)
73         */
74        0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
75        0xFFFFFC84, 0xFFFFFC07, /* last */
76                                _NOT_USED_, _NOT_USED_,
77        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
78        /*
79         * Exception. (Offset 3c in UPMA RAM)
80         */
81        0x7FFFFC07, /* last */
82                    _NOT_USED_, _NOT_USED_, _NOT_USED_,
83};
84
85/* ------------------------------------------------------------------------- */
86
87
88/*
89 * Check Board Identity:
90 *
91 * Always return 1 (no second DRAM bank).
92 */
93
94int checkboard (void)
95{
96        char *s = getenv ("serial#");
97
98        puts ("Board: RRvision ");
99
100        for (; s && *s; ++s) {
101                if (*s == ' ')
102                        break;
103                putc (*s);
104        }
105
106        putc ('\n');
107
108        return (0);
109}
110
111/* ------------------------------------------------------------------------- */
112
113phys_size_t initdram (int board_type)
114{
115        volatile immap_t *immap = (immap_t *) CFG_IMMR;
116        volatile memctl8xx_t *memctl = &immap->im_memctl;
117        unsigned long reg;
118        long int size8, size9;
119        long int size = 0;
120
121        upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table) / sizeof(uint));
122
123        /*
124         * Preliminary prescaler for refresh (depends on number of
125         * banks): This value is selected for four cycles every 62.4 us
126         * with two SDRAM banks or four cycles every 31.2 us with one
127         * bank. It will be adjusted after memory sizing.
128         */
129        memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
130
131        memctl->memc_mar = 0x00000088;
132
133        /*
134         * Map controller bank 1 the SDRAM bank 2 at physical address 0.
135         */
136        memctl->memc_or1 = CFG_OR2_PRELIM;
137        memctl->memc_br1 = CFG_BR2_PRELIM;
138
139        memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));     /* no refresh yet */
140
141        udelay (200);
142
143        /* perform SDRAM initializsation sequence */
144
145        memctl->memc_mcr = 0x80002105;  /* SDRAM bank 0 */
146        udelay (1);
147        memctl->memc_mcr = 0x80002230;  /* SDRAM bank 0 - execute twice */
148        udelay (1);
149
150        memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
151
152        udelay (1000);
153
154        /*
155         * Check Bank 0 Memory Size
156         *
157         * try 8 column mode
158         */
159        size8 = dram_size (CFG_MAMR_8COL,
160                           SDRAM_BASE2_PRELIM,
161                           SDRAM_MAX_SIZE);
162
163        udelay (1000);
164
165        /*
166         * try 9 column mode
167         */
168        size9 = dram_size (CFG_MAMR_9COL,
169                           SDRAM_BASE2_PRELIM,
170                           SDRAM_MAX_SIZE);
171
172        if (size8 < size9) {            /* leave configuration at 9 columns */
173                size = size9;
174/*              debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);  */
175        } else {                        /* back to 8 columns            */
176                size = size8;
177                memctl->memc_mamr = CFG_MAMR_8COL;
178                udelay (500);
179/*              debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);  */
180        }
181
182        udelay (1000);
183
184        /*
185         * Adjust refresh rate depending on SDRAM type
186         * For types > 128 MBit leave it at the current (fast) rate
187         */
188        if (size < 0x02000000) {
189                /* reduce to 15.6 us (62.4 us / quad) */
190                memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
191                udelay (1000);
192        }
193
194        /*
195         * Final mapping
196         */
197        memctl->memc_or1 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
198        memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
199
200        /*
201         * No bank 1
202         *
203         * invalidate bank
204         */
205        memctl->memc_br3 = 0;
206
207        /* adjust refresh rate depending on SDRAM type, one bank */
208        reg = memctl->memc_mptpr;
209        reg >>= 1;                      /* reduce to CFG_MPTPR_1BK_8K / _4K */
210        memctl->memc_mptpr = reg;
211
212        udelay (10000);
213
214        return (size);
215}
216
217/* ------------------------------------------------------------------------- */
218
219/*
220 * Check memory range for valid RAM. A simple memory test determines
221 * the actually available RAM size between addresses `base' and
222 * `base + maxsize'. Some (not all) hardware errors are detected:
223 * - short between address lines
224 * - short between data lines
225 */
226
227static long int dram_size (long int mamr_value, long int *base,
228                                                   long int maxsize)
229{
230        volatile immap_t *immap = (immap_t *) CFG_IMMR;
231        volatile memctl8xx_t *memctl = &immap->im_memctl;
232
233        memctl->memc_mamr = mamr_value;
234
235        return (get_ram_size(base, maxsize));
236}
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