source: SVN/rincon/u-boot/board/RRvision/video_ad7179.h @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 2.3 KB
Line 
1/*
2 * (C) Copyright 2003 Wolfgang Grandegger <wg@denx.de>
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#define VIDEO_ENCODER_NAME      "Analog Devices AD7179"
24
25#define VIDEO_ENCODER_I2C_RATE  100000  /* Max rate is 100Khz   */
26#define VIDEO_ENCODER_CB_Y_CR_Y         /* Use CB Y CR Y format...      */
27
28#define VIDEO_MODE_YUYV         /* The only mode supported by this encoder      */
29#undef  VIDEO_MODE_RGB
30#define VIDEO_MODE_BPP          16
31
32#ifdef  VIDEO_MODE_PAL
33#define VIDEO_ACTIVE_COLS       720
34#define VIDEO_ACTIVE_ROWS       576
35#define VIDEO_VISIBLE_COLS      640
36#define VIDEO_VISIBLE_ROWS      480
37#else
38#error "NTSC mode is not supported"
39#endif
40
41static unsigned char video_encoder_data[] = {
42                                0x05, /* Mode Register 0 */
43                                0x11, /* Mode Register 1 */
44                                0x20, /* Mode Register 2 */
45                                0x0C, /* Mode Register 3 */
46                                0x01, /* Mode Register 4 */
47                                0x00, /* Reserved */
48                                0x00, /* Reserved */
49                                0x04, /* Timing Register 0 */
50                                0x00, /* Timing Register 1 */
51                                0xCB, /* Subcarrier Frequency Register 0 */
52                                0x0A, /* Subcarrier Frequency Register 1 */
53                                0x09, /* Subcarrier Frequency Register 2 */
54                                0x2A, /* Subcarrier Frequency Register 3 */
55                                0x00, /* Subcarrier Phase */
56                                0x00, /* Closed Captioning Ext Reg 0 */
57                                0x00, /* Closed Captioning Ext Reg 1 */
58                                0x00, /* Closed Captioning Reg 0 */
59                                0x00, /* Closed Captioning Reg 1 */
60                                0x00, /* Pedestal Control Reg 0 */
61                                0x00, /* Pedestal Control Reg 1 */
62                                0x00, /* Pedestal Control Reg 2 */
63                                0x00, /* Pedestal Control Reg 3 */
64                                0x00, /* CGMS_WSS Reg 0 */
65                                0x00, /* CGMS_WSS Reg 0 */
66                                0x00, /* CGMS_WSS Reg 0 */
67                                0x00  /* Teletext Req. Control Reg */
68} ;
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