source: SVN/rincon/u-boot/board/amcc/acadia/memory.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 2 years ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 2.9 KB
Line 
1/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* define DEBUG for debugging output (obviously ;-)) */
25#if 0
26#define DEBUG
27#endif
28
29#include <common.h>
30#include <asm/processor.h>
31#include <asm/io.h>
32#include <asm/gpio.h>
33
34extern void board_pll_init_f(void);
35
36#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
37static void cram_bcr_write(u32 wr_val)
38{
39        wr_val <<= 2;
40
41        /* set CRAM_CRE to 1 */
42        gpio_write_bit(CFG_GPIO_CRAM_CRE, 1);
43
44        /* Write BCR to CRAM on CS1 */
45        out32(wr_val + 0x00200000, 0);
46        debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000);
47
48        /* Write BCR to CRAM on CS2 */
49        out32(wr_val + 0x02200000, 0);
50        debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000);
51
52        sync();
53        eieio();
54
55        /* set CRAM_CRE back to 0 (normal operation) */
56        gpio_write_bit(CFG_GPIO_CRAM_CRE, 0);
57
58        return;
59}
60#endif
61
62phys_size_t initdram(int board_type)
63{
64#if defined(CONFIG_NAND_SPL)
65        u32 reg;
66
67        /* don't reinit PLL when booting via I2C bootstrap option */
68        mfsdr(SDR_PINSTP, reg);
69        if (reg != 0xf0000000)
70                board_pll_init_f();
71#endif
72
73#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
74        int i;
75        u32 val;
76
77        /* 1. EBC need to program READY, CLK, ADV for ASync mode */
78        gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
79        gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
80        gpio_config(CFG_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
81        gpio_config(CFG_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
82
83        /* 2. EBC in Async mode */
84        mtebc(pb1ap, 0x078F1EC0);
85        mtebc(pb2ap, 0x078F1EC0);
86        mtebc(pb1cr, 0x000BC000);
87        mtebc(pb2cr, 0x020BC000);
88
89        /* 3. Set CRAM in Sync mode */
90        cram_bcr_write(0x7012);         /* CRAM burst setting */
91
92        /* 4. EBC in Sync mode */
93        mtebc(pb1ap, 0x9C0201C0);
94        mtebc(pb2ap, 0x9C0201C0);
95
96        /* Set GPIO pins back to alternate function */
97        gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
98        gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
99
100        /* Config EBC to use RDY */
101        mfsdr(sdrultra0, val);
102        mtsdr(sdrultra0, val | SDR_ULTRA0_EBCRDYEN);
103
104        /* Wait a short while, since for NAND booting this is too fast */
105        for (i=0; i<200000; i++)
106                ;
107#endif
108
109        return (CFG_MBYTES_RAM << 20);
110}
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