source: SVN/rincon/u-boot/board/amcc/bamboo/init.S @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 3.4 KB
Line 
1/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <ppc_asm.tmpl>
27#include <config.h>
28#include <asm-ppc/mmu.h>
29
30/**************************************************************************
31 * TLB TABLE
32 *
33 * This table is used by the cpu boot code to setup the initial tlb
34 * entries. Rather than make broad assumptions in the cpu source tree,
35 * this table lets each board set things up however they like.
36 *
37 *  Pointer to the table is returned in r1
38 *
39 *************************************************************************/
40        .section .bootpg,"ax"
41        .globl tlbtab
42
43tlbtab:
44        tlbtab_start
45
46        /*
47         * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
48         * speed up boot process. It is patched after relocation to enable SA_I
49         */
50#ifndef CONFIG_NAND_SPL
51        tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
52#else
53        tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G)
54        tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
55#endif
56
57        /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
58        tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
59
60        /* PCI base & peripherals */
61        tlbentry(CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I)
62
63        tlbentry(CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
64        tlbentry(CFG_NAND_ADDR, SZ_4K, CFG_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
65
66        /* PCI */
67        tlbentry(CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I)
68        tlbentry(CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I)
69        tlbentry(CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I)
70        tlbentry(CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I)
71
72        /* USB 2.0 Device */
73        tlbentry(CFG_USB_DEVICE, SZ_1K, CFG_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I)
74
75        tlbtab_end
76
77#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
78        /*
79         * For NAND booting the first TLB has to be reconfigured to full size
80         * and with caching disabled after running from RAM!
81         */
82#define TLB00   TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
83#define TLB01   TLB1(CFG_BOOT_BASE_ADDR, 0)
84#define TLB02   TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
85
86        .globl  reconfig_tlb0
87reconfig_tlb0:
88        sync
89        isync
90        addi    r4,r0,0x0000            /* TLB entry #0 */
91        lis     r5,TLB00@h
92        ori     r5,r5,TLB00@l
93        tlbwe   r5,r4,0x0000            /* Save it out */
94        lis     r5,TLB01@h
95        ori     r5,r5,TLB01@l
96        tlbwe   r5,r4,0x0001            /* Save it out */
97        lis     r5,TLB02@h
98        ori     r5,r5,TLB02@l
99        tlbwe   r5,r4,0x0002            /* Save it out */
100        sync
101        isync
102        blr
103#endif
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