source: SVN/rincon/u-boot/board/amcc/sequoia/sequoia.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 15.3 KB
Line 
1/*
2 * (C) Copyright 2006-2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2006
6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
7 * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <libfdt.h>
27#include <fdt_support.h>
28#include <ppc4xx.h>
29#include <asm/gpio.h>
30#include <asm/processor.h>
31#include <asm/io.h>
32#include <asm/bitops.h>
33
34DECLARE_GLOBAL_DATA_PTR;
35
36extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
37
38ulong flash_get_size (ulong base, int banknum);
39
40int board_early_init_f(void)
41{
42        u32 sdr0_cust0;
43        u32 sdr0_pfc1, sdr0_pfc2;
44        u32 reg;
45
46        mtdcr(ebccfga, xbcfg);
47        mtdcr(ebccfgd, 0xb8400000);
48
49        /*
50         * Setup the interrupt controller polarities, triggers, etc.
51         */
52        mtdcr(uic0sr, 0xffffffff);      /* clear all */
53        mtdcr(uic0er, 0x00000000);      /* disable all */
54        mtdcr(uic0cr, 0x00000005);      /* ATI & UIC1 crit are critical */
55        mtdcr(uic0pr, 0xfffff7ff);      /* per ref-board manual */
56        mtdcr(uic0tr, 0x00000000);      /* per ref-board manual */
57        mtdcr(uic0vr, 0x00000000);      /* int31 highest, base=0x000 */
58        mtdcr(uic0sr, 0xffffffff);      /* clear all */
59
60        mtdcr(uic1sr, 0xffffffff);      /* clear all */
61        mtdcr(uic1er, 0x00000000);      /* disable all */
62        mtdcr(uic1cr, 0x00000000);      /* all non-critical */
63        mtdcr(uic1pr, 0xffffffff);      /* per ref-board manual */
64        mtdcr(uic1tr, 0x00000000);      /* per ref-board manual */
65        mtdcr(uic1vr, 0x00000000);      /* int31 highest, base=0x000 */
66        mtdcr(uic1sr, 0xffffffff);      /* clear all */
67
68        mtdcr(uic2sr, 0xffffffff);      /* clear all */
69        mtdcr(uic2er, 0x00000000);      /* disable all */
70        mtdcr(uic2cr, 0x00000000);      /* all non-critical */
71        mtdcr(uic2pr, 0xffffffff);      /* per ref-board manual */
72        mtdcr(uic2tr, 0x00000000);      /* per ref-board manual */
73        mtdcr(uic2vr, 0x00000000);      /* int31 highest, base=0x000 */
74        mtdcr(uic2sr, 0xffffffff);      /* clear all */
75
76        /* 50MHz tmrclk */
77        out_8((u8 *) CFG_BCSR_BASE + 0x04, 0x00);
78
79        /* clear write protects */
80        out_8((u8 *) CFG_BCSR_BASE + 0x07, 0x00);
81
82        /* enable Ethernet */
83        out_8((u8 *) CFG_BCSR_BASE + 0x08, 0x00);
84
85        /* enable USB device */
86        out_8((u8 *) CFG_BCSR_BASE + 0x09, 0x20);
87
88        /* select Ethernet (and optionally IIC1) pins */
89        mfsdr(SDR0_PFC1, sdr0_pfc1);
90        sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
91                SDR0_PFC1_SELECT_CONFIG_4;
92#ifdef CONFIG_I2C_MULTI_BUS
93        sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
94#endif
95        /* Two UARTs, so we need 4-pin mode.  Also, we want CTS/RTS mode. */
96        sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
97        sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS;
98        sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS;
99
100        mfsdr(SDR0_PFC2, sdr0_pfc2);
101        sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
102                SDR0_PFC2_SELECT_CONFIG_4;
103        mtsdr(SDR0_PFC2, sdr0_pfc2);
104        mtsdr(SDR0_PFC1, sdr0_pfc1);
105
106        /* PCI arbiter enabled */
107        mfsdr(sdr_pci0, reg);
108        mtsdr(sdr_pci0, 0x80000000 | reg);
109
110        /* setup NAND FLASH */
111        mfsdr(SDR0_CUST0, sdr0_cust0);
112        sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL    |
113                SDR0_CUST0_NDFC_ENABLE          |
114                SDR0_CUST0_NDFC_BW_8_BIT        |
115                SDR0_CUST0_NDFC_ARE_MASK        |
116                (0x80000000 >> (28 + CFG_NAND_CS));
117        mtsdr(SDR0_CUST0, sdr0_cust0);
118
119        return 0;
120}
121
122int misc_init_r(void)
123{
124        uint pbcr;
125        int size_val = 0;
126        u32 reg;
127#ifdef CONFIG_440EPX
128        unsigned long usb2d0cr = 0;
129        unsigned long usb2phy0cr, usb2h0cr = 0;
130        unsigned long sdr0_pfc1;
131        char *act = getenv("usbact");
132#endif
133
134        /* Re-do flash sizing to get full correct info */
135
136        /* adjust flash start and offset */
137        gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
138        gd->bd->bi_flashoffset = 0;
139
140#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
141        mtdcr(ebccfga, pb3cr);
142#else
143        mtdcr(ebccfga, pb0cr);
144#endif
145        pbcr = mfdcr(ebccfgd);
146        size_val = ffs(gd->bd->bi_flashsize) - 21;
147        pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
148#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
149        mtdcr(ebccfga, pb3cr);
150#else
151        mtdcr(ebccfga, pb0cr);
152#endif
153        mtdcr(ebccfgd, pbcr);
154
155        /*
156         * Re-check to get correct base address
157         */
158        flash_get_size(gd->bd->bi_flashstart, 0);
159
160#ifdef CONFIG_ENV_IS_IN_FLASH
161        /* Monitor protection ON by default */
162        (void)flash_protect(FLAG_PROTECT_SET,
163                            -CFG_MONITOR_LEN,
164                            0xffffffff,
165                            &flash_info[0]);
166
167        /* Env protection ON by default */
168        (void)flash_protect(FLAG_PROTECT_SET,
169                            CONFIG_ENV_ADDR_REDUND,
170                            CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
171                            &flash_info[0]);
172#endif
173
174        /*
175         * USB suff...
176         */
177#ifdef CONFIG_440EPX
178        if (act == NULL || strcmp(act, "hostdev") == 0) {
179                /* SDR Setting */
180                mfsdr(SDR0_PFC1, sdr0_pfc1);
181                mfsdr(SDR0_USB2D0CR, usb2d0cr);
182                mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
183                mfsdr(SDR0_USB2H0CR, usb2h0cr);
184
185                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
186                usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
187                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
188                usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
189                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
190                usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
191                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
192                usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
193                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
194                usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
195
196                /*
197                 * An 8-bit/60MHz interface is the only possible alternative
198                 * when connecting the Device to the PHY
199                 */
200                usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
201                usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
202
203                /*
204                 * To enable the USB 2.0 Device function
205                 * through the UTMI interface
206                 */
207                usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
208                usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
209
210                sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
211                sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
212
213                mtsdr(SDR0_PFC1, sdr0_pfc1);
214                mtsdr(SDR0_USB2D0CR, usb2d0cr);
215                mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
216                mtsdr(SDR0_USB2H0CR, usb2h0cr);
217
218                /*clear resets*/
219                udelay (1000);
220                mtsdr(SDR0_SRST1, 0x00000000);
221                udelay (1000);
222                mtsdr(SDR0_SRST0, 0x00000000);
223
224                printf("USB:   Host(int phy) Device(ext phy)\n");
225
226        } else if (strcmp(act, "dev") == 0) {
227                /*-------------------PATCH-------------------------------*/
228                mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
229
230                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
231                usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
232                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
233                usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
234                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
235                usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
236                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
237                usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
238                mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
239
240                udelay (1000);
241                mtsdr(SDR0_SRST1, 0x672c6000);
242
243                udelay (1000);
244                mtsdr(SDR0_SRST0, 0x00000080);
245
246                udelay (1000);
247                mtsdr(SDR0_SRST1, 0x60206000);
248
249                *(unsigned int *)(0xe0000350) = 0x00000001;
250
251                udelay (1000);
252                mtsdr(SDR0_SRST1, 0x60306000);
253                /*-------------------PATCH-------------------------------*/
254
255                /* SDR Setting */
256                mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
257                mfsdr(SDR0_USB2H0CR, usb2h0cr);
258                mfsdr(SDR0_USB2D0CR, usb2d0cr);
259                mfsdr(SDR0_PFC1, sdr0_pfc1);
260
261                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
262                usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
263                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
264                usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
265                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
266                usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
267                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
268                usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
269                usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
270                usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
271
272                usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
273                usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
274
275                usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
276                usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
277
278                sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
279                sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
280
281                mtsdr(SDR0_USB2H0CR, usb2h0cr);
282                mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
283                mtsdr(SDR0_USB2D0CR, usb2d0cr);
284                mtsdr(SDR0_PFC1, sdr0_pfc1);
285
286                /* clear resets */
287                udelay (1000);
288                mtsdr(SDR0_SRST1, 0x00000000);
289                udelay (1000);
290                mtsdr(SDR0_SRST0, 0x00000000);
291
292                printf("USB:   Device(int phy)\n");
293        }
294#endif /* CONFIG_440EPX */
295
296        mfsdr(SDR0_SRST1, reg);         /* enable security/kasumi engines */
297        reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
298        mtsdr(SDR0_SRST1, reg);
299
300        /*
301         * Clear PLB4A0_ACR[WRP]
302         * This fix will make the MAL burst disabling patch for the Linux
303         * EMAC driver obsolete.
304         */
305        reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
306        mtdcr(plb4_acr, reg);
307
308        return 0;
309}
310
311int checkboard(void)
312{
313        char *s = getenv("serial#");
314        u8 rev;
315        u8 val;
316
317#ifdef CONFIG_440EPX
318        printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
319#else
320        printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
321#endif
322
323        rev = in_8((void *)(CFG_BCSR_BASE + 0));
324        val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
325        printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
326
327        if (s != NULL) {
328                puts(", serial# ");
329                puts(s);
330        }
331        putc('\n');
332
333        return (0);
334}
335
336#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
337/*
338 * Assign interrupts to PCI devices.
339 */
340void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
341{
342        pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
343}
344#endif
345
346/*
347 * pci_pre_init
348 *
349 * This routine is called just prior to registering the hose and gives
350 * the board the opportunity to check things. Returning a value of zero
351 * indicates that things are bad & PCI initialization should be aborted.
352 *
353 * Different boards may wish to customize the pci controller structure
354 * (add regions, override default access routines, etc) or perform
355 * certain pre-initialization actions.
356 */
357#if defined(CONFIG_PCI)
358int pci_pre_init(struct pci_controller *hose)
359{
360        unsigned long addr;
361
362        /*
363         * Set priority for all PLB3 devices to 0.
364         * Set PLB3 arbiter to fair mode.
365         */
366        mfsdr(sdr_amp1, addr);
367        mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
368        addr = mfdcr(plb3_acr);
369        mtdcr(plb3_acr, addr | 0x80000000);
370
371        /*
372         * Set priority for all PLB4 devices to 0.
373         */
374        mfsdr(sdr_amp0, addr);
375        mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
376        addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
377        mtdcr(plb4_acr, addr);
378
379        /*
380         * Set Nebula PLB4 arbiter to fair mode.
381         */
382        /* Segment0 */
383        addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
384        addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
385        addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
386        addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
387        mtdcr(plb0_acr, addr);
388
389        /* Segment1 */
390        addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
391        addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
392        addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
393        addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
394        mtdcr(plb1_acr, addr);
395
396#ifdef CONFIG_PCI_PNP
397        hose->fixup_irq = sequoia_pci_fixup_irq;
398#endif
399        return 1;
400}
401#endif /* defined(CONFIG_PCI) */
402
403/*
404 * pci_target_init
405 *
406 * The bootstrap configuration provides default settings for the pci
407 * inbound map (PIM). But the bootstrap config choices are limited and
408 * may not be sufficient for a given board.
409 */
410#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
411void pci_target_init(struct pci_controller *hose)
412{
413        /*
414         * Set up Direct MMIO registers
415         */
416        /*
417         * PowerPC440EPX PCI Master configuration.
418         * Map one 1Gig range of PLB/processor addresses to PCI memory space.
419         * PLB address 0xA0000000-0xDFFFFFFF
420         *     ==> PCI address 0xA0000000-0xDFFFFFFF
421         * Use byte reversed out routines to handle endianess.
422         * Make this region non-prefetchable.
423         */
424        out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
425                                                /* - disabled b4 setting */
426        out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);  /* PMM0 Local Address */
427        out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
428        out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
429        out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, */
430                                                /* and enable region */
431
432        out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute */
433                                                /* - disabled b4 setting */
434        out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
435        out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
436        out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
437        out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, */
438                                                /* and enable region */
439
440        out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
441        out32r(PCIX0_PTM1LA, 0);                /* Local Addr. Reg */
442        out32r(PCIX0_PTM2MS, 0);                /* Memory Size/Attribute */
443        out32r(PCIX0_PTM2LA, 0);                /* Local Addr. Reg */
444
445        /*
446         * Set up Configuration registers
447         */
448
449        /* Program the board's subsystem id/vendor id */
450        pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
451                              CFG_PCI_SUBSYS_VENDORID);
452        pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
453
454        /* Configure command register as bus master */
455        pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
456
457        /* 240nS PCI clock */
458        pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
459
460        /* No error reporting */
461        pci_write_config_word(0, PCI_ERREN, 0);
462
463        pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
464
465}
466#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
467
468#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
469void pci_master_init(struct pci_controller *hose)
470{
471        unsigned short temp_short;
472
473        /*
474         * Write the PowerPC440 EP PCI Configuration regs.
475         * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
476         * Enable PowerPC440 EP to act as a PCI memory target (PTM).
477         */
478        pci_read_config_word(0, PCI_COMMAND, &temp_short);
479        pci_write_config_word(0, PCI_COMMAND,
480                              temp_short | PCI_COMMAND_MASTER |
481                              PCI_COMMAND_MEMORY);
482}
483#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
484
485/*
486 * is_pci_host
487 *
488 * This routine is called to determine if a pci scan should be
489 * performed. With various hardware environments (especially cPCI and
490 * PPMC) it's insufficient to depend on the state of the arbiter enable
491 * bit in the strap register, or generic host/adapter assumptions.
492 *
493 * Rather than hard-code a bad assumption in the general 440 code, the
494 * 440 pci code requires the board to decide at runtime.
495 *
496 * Return 0 for adapter mode, non-zero for host (monarch) mode.
497 */
498#if defined(CONFIG_PCI)
499int is_pci_host(struct pci_controller *hose)
500{
501        /* Cactus is always configured as host. */
502        return (1);
503}
504#endif /* defined(CONFIG_PCI) */
505
506#if defined(CONFIG_POST)
507/*
508 * Returns 1 if keys pressed to start the power-on long-running tests
509 * Called from board_init_f().
510 */
511int post_hotkeys_pressed(void)
512{
513        return 0;       /* No hotkeys supported */
514}
515#endif /* CONFIG_POST */
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