source: SVN/rincon/u-boot/board/apollon/apollon.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 15.8 KB
Line 
1/*
2 * (C) Copyright 2005-2007
3 * Samsung Electronics.
4 * Kyungmin Park <kyungmin.park@samsung.com>
5 *
6 * Derived from omap2420
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26#include <common.h>
27#include <asm/arch/omap2420.h>
28#include <asm/io.h>
29#include <asm/arch/bits.h>
30#include <asm/arch/mux.h>
31#include <asm/arch/sys_proto.h>
32#include <asm/arch/sys_info.h>
33#include <asm/arch/mem.h>
34#include <asm/mach-types.h>
35
36void wait_for_command_complete(unsigned int wd_base);
37
38DECLARE_GLOBAL_DATA_PTR;
39
40#define write_config_reg(reg, value)                                    \
41do {                                                                    \
42        writeb(value, reg);                                             \
43} while (0)
44
45#define mask_config_reg(reg, mask)                                      \
46do {                                                                    \
47        char value = readb(reg) & ~(mask);                              \
48        writeb(value, reg);                                             \
49} while (0)
50
51/*******************************************************
52 * Routine: delay
53 * Description: spinning delay to use before udelay works
54 ******************************************************/
55static inline void delay(unsigned long loops)
56{
57        __asm__("1:\n" "subs %0, %1, #1\n"
58                  "bne 1b":"=r" (loops):"0"(loops));
59}
60
61/*****************************************
62 * Routine: board_init
63 * Description: Early hardware init.
64 *****************************************/
65int board_init(void)
66{
67        gpmc_init();            /* in SRAM or SDRM, finish GPMC */
68
69        gd->bd->bi_arch_number = 919;
70        /* adress of boot parameters */
71        gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0 + 0x100);
72
73        return 0;
74}
75
76/**********************************************************
77 * Routine: s_init
78 * Description: Does early system init of muxing and clocks.
79 * - Called path is with sram stack.
80 **********************************************************/
81void s_init(void)
82{
83        watchdog_init();
84        set_muxconf_regs();
85        delay(100);
86
87        peripheral_enable();
88        icache_enable();
89}
90
91/*******************************************************
92 * Routine: misc_init_r
93 * Description: Init ethernet (done here so udelay works)
94 ********************************************************/
95int misc_init_r(void)
96{
97        ether_init();           /* better done here so timers are init'ed */
98        return (0);
99}
100
101/****************************************
102 * Routine: watchdog_init
103 * Description: Shut down watch dogs
104 *****************************************/
105void watchdog_init(void)
106{
107        /* There are 4 watch dogs.  1 secure, and 3 general purpose.
108         * The ROM takes care of the secure one. Of the 3 GP ones,
109         * 1 can reset us directly, the other 2 only generate MPU interrupts.
110         */
111        __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
112        wait_for_command_complete(WD2_BASE);
113        __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
114
115#define MPU_WD_CLOCKED 1
116#if MPU_WD_CLOCKED
117        /* value 0x10 stick on aptix, BIT4 polarity seems oppsite */
118        __raw_writel(WD_UNLOCK1, WD3_BASE + WSPR);
119        wait_for_command_complete(WD3_BASE);
120        __raw_writel(WD_UNLOCK2, WD3_BASE + WSPR);
121
122        __raw_writel(WD_UNLOCK1, WD4_BASE + WSPR);
123        wait_for_command_complete(WD4_BASE);
124        __raw_writel(WD_UNLOCK2, WD4_BASE + WSPR);
125#endif
126}
127
128/******************************************************
129 * Routine: wait_for_command_complete
130 * Description: Wait for posting to finish on watchdog
131 ******************************************************/
132void wait_for_command_complete(unsigned int wd_base)
133{
134        int pending = 1;
135        do {
136                pending = __raw_readl(wd_base + WWPS);
137        } while (pending);
138}
139
140/*******************************************************************
141 * Routine:ether_init
142 * Description: take the Ethernet controller out of reset and wait
143 *                 for the EEPROM load to complete.
144 ******************************************************************/
145void ether_init(void)
146{
147#ifdef CONFIG_DRIVER_LAN91C96
148        int cnt = 20;
149
150        __raw_writeb(0x03, OMAP2420_CTRL_BASE + 0x0f2); /*protect->gpio74 */
151
152        __raw_writew(0x0, LAN_RESET_REGISTER);
153        do {
154                __raw_writew(0x1, LAN_RESET_REGISTER);
155                udelay(100);
156                if (cnt == 0)
157                        goto eth_reset_err_out;
158                --cnt;
159        } while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
160
161        cnt = 20;
162
163        do {
164                __raw_writew(0x0, LAN_RESET_REGISTER);
165                udelay(100);
166                if (cnt == 0)
167                        goto eth_reset_err_out;
168                --cnt;
169        } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
170        udelay(1000);
171
172        mask_config_reg(ETH_CONTROL_REG, 0x01);
173        udelay(1000);
174
175eth_reset_err_out:
176        return;
177#endif
178}
179
180/**********************************************
181 * Routine: dram_init
182 * Description: sets uboots idea of sdram size
183 **********************************************/
184int dram_init(void)
185{
186        unsigned int size0 = 0, size1 = 0;
187        u32 mtype, btype, rev = 0, cpu = 0;
188#define NOT_EARLY 0
189
190        btype = get_board_type();
191        mtype = get_mem_type();
192        rev = get_cpu_rev();
193        cpu = get_cpu_type();
194
195        display_board_info(btype);
196
197        if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
198                /* init other chip select */
199                do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
200        }
201
202        size0 = get_sdr_cs_size(SDRC_CS0_OSET);
203        size1 = get_sdr_cs_size(SDRC_CS1_OSET);
204
205        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
206        gd->bd->bi_dram[0].size = size0;
207#if CONFIG_NR_DRAM_BANKS > 1
208        gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + size0;
209        gd->bd->bi_dram[1].size = size1;
210#endif
211
212        return 0;
213}
214
215/**********************************************************
216 * Routine: set_muxconf_regs
217 * Description: Setting up the configuration Mux registers
218 *              specific to the hardware
219 *********************************************************/
220void set_muxconf_regs(void)
221{
222        muxSetupSDRC();
223        muxSetupGPMC();
224        muxSetupUsb0();         /* USB Device */
225        muxSetupUsbHost();      /* USB Host */
226        muxSetupUART1();
227        muxSetupLCD();
228        muxSetupMMCSD();
229        muxSetupTouchScreen();
230}
231
232/*****************************************************************
233 * Routine: peripheral_enable
234 * Description: Enable the clks & power for perifs (GPT2, UART1,...)
235 ******************************************************************/
236void peripheral_enable(void)
237{
238        unsigned int v, if_clks = 0, func_clks = 0;
239
240        /* Enable GP2 timer. */
241        if_clks |= BIT4 | BIT3;
242        func_clks |= BIT4 | BIT3;
243        /* Sys_clk input OMAP2420_GPT2 */
244        v = __raw_readl(CM_CLKSEL2_CORE) | 0x4 | 0x2;
245        __raw_writel(v, CM_CLKSEL2_CORE);
246        __raw_writel(0x1, CM_CLKSEL_WKUP);
247
248#ifdef CFG_NS16550
249        /* Enable UART1 clock */
250        func_clks |= BIT21;
251        if_clks |= BIT21;
252#endif
253        /* Interface clocks on */
254        v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;
255        __raw_writel(v, CM_ICLKEN1_CORE);
256        /* Functional Clocks on */
257        v = __raw_readl(CM_FCLKEN1_CORE) | func_clks;
258        __raw_writel(v, CM_FCLKEN1_CORE);
259        delay(1000);
260
261#ifndef KERNEL_UPDATED
262        {
263#define V1 0xffffffff
264#define V2 0x00000007
265
266                __raw_writel(V1, CM_FCLKEN1_CORE);
267                __raw_writel(V2, CM_FCLKEN2_CORE);
268                __raw_writel(V1, CM_ICLKEN1_CORE);
269                __raw_writel(V1, CM_ICLKEN2_CORE);
270        }
271#endif
272}
273
274/****************************************
275 * Routine: muxSetupUsb0   (ostboot)
276 * Description: Setup usb muxing
277 *****************************************/
278void muxSetupUsb0(void)
279{
280        mask_config_reg(CONTROL_PADCONF_USB0_PUEN, 0x1f);
281        mask_config_reg(CONTROL_PADCONF_USB0_VP, 0x1f);
282        mask_config_reg(CONTROL_PADCONF_USB0_VM, 0x1f);
283        mask_config_reg(CONTROL_PADCONF_USB0_RCV, 0x1f);
284        mask_config_reg(CONTROL_PADCONF_USB0_TXEN, 0x1f);
285        mask_config_reg(CONTROL_PADCONF_USB0_SE0, 0x1f);
286        mask_config_reg(CONTROL_PADCONF_USB0_DAT, 0x1f);
287}
288
289/****************************************
290 * Routine: muxSetupUSBHost   (ostboot)
291 * Description: Setup USB Host muxing
292 *****************************************/
293void muxSetupUsbHost(void)
294{
295        /* V19 */
296        write_config_reg(CONTROL_PADCONF_USB1_RCV, 1);
297        /* W20 */
298        write_config_reg(CONTROL_PADCONF_USB1_TXEN, 1);
299        /* N14 */
300        write_config_reg(CONTROL_PADCONF_GPIO69, 3);
301        /* P15 */
302        write_config_reg(CONTROL_PADCONF_GPIO70, 3);
303        /* L18 */
304        write_config_reg(CONTROL_PADCONF_GPIO102, 3);
305        /* L19 */
306        write_config_reg(CONTROL_PADCONF_GPIO103, 3);
307        /* K15 */
308        write_config_reg(CONTROL_PADCONF_GPIO104, 3);
309        /* K14 */
310        write_config_reg(CONTROL_PADCONF_GPIO105, 3);
311}
312
313/****************************************
314 * Routine: muxSetupUART1  (ostboot)
315 * Description: Set up uart1 muxing
316 *****************************************/
317void muxSetupUART1(void)
318{
319        /* UART1_CTS pin configuration, PIN = D21, Mode = 0, PUPD=Disabled */
320        write_config_reg(CONTROL_PADCONF_UART1_CTS, 0);
321        /* UART1_RTS pin configuration, PIN = H21, Mode = 0, PUPD=Disabled */
322        write_config_reg(CONTROL_PADCONF_UART1_RTS, 0);
323        /* UART1_TX pin configuration, PIN = L20, Mode = 0, PUPD=Disabled */
324        write_config_reg(CONTROL_PADCONF_UART1_TX, 0);
325        /* UART1_RX pin configuration, PIN = T21, Mode = 0, PUPD=Disabled */
326        write_config_reg(CONTROL_PADCONF_UART1_RX, 0);
327}
328
329/****************************************
330 * Routine: muxSetupLCD   (ostboot)
331 * Description: Setup lcd muxing
332 *****************************************/
333void muxSetupLCD(void)
334{
335        /* LCD_D0 pin configuration, PIN = Y7, Mode = 0, PUPD=Disabled */
336        write_config_reg(CONTROL_PADCONF_DSS_D0, 0);
337        /* LCD_D1 pin configuration, PIN = P10 , Mode = 0, PUPD=Disabled */
338        write_config_reg(CONTROL_PADCONF_DSS_D1, 0);
339        /* LCD_D2 pin configuration, PIN = V8, Mode = 0, PUPD=Disabled */
340        write_config_reg(CONTROL_PADCONF_DSS_D2, 0);
341        /* LCD_D3 pin configuration, PIN = Y8, Mode = 0, PUPD=Disabled */
342        write_config_reg(CONTROL_PADCONF_DSS_D3, 0);
343        /* LCD_D4 pin configuration, PIN = W8, Mode = 0, PUPD=Disabled */
344        write_config_reg(CONTROL_PADCONF_DSS_D4, 0);
345        /* LCD_D5 pin configuration, PIN = R10, Mode = 0, PUPD=Disabled */
346        write_config_reg(CONTROL_PADCONF_DSS_D5, 0);
347        /* LCD_D6 pin configuration, PIN = Y9, Mode = 0, PUPD=Disabled */
348        write_config_reg(CONTROL_PADCONF_DSS_D6, 0);
349        /* LCD_D7 pin configuration, PIN = V9, Mode = 0, PUPD=Disabled */
350        write_config_reg(CONTROL_PADCONF_DSS_D7, 0);
351        /* LCD_D8 pin configuration, PIN = W9, Mode = 0, PUPD=Disabled */
352        write_config_reg(CONTROL_PADCONF_DSS_D8, 0);
353        /* LCD_D9 pin configuration, PIN = P11, Mode = 0, PUPD=Disabled */
354        write_config_reg(CONTROL_PADCONF_DSS_D9, 0);
355        /* LCD_D10 pin configuration, PIN = V10, Mode = 0, PUPD=Disabled */
356        write_config_reg(CONTROL_PADCONF_DSS_D10, 0);
357        /* LCD_D11 pin configuration, PIN = Y10, Mode = 0, PUPD=Disabled */
358        write_config_reg(CONTROL_PADCONF_DSS_D11, 0);
359        /* LCD_D12 pin configuration, PIN = W10, Mode = 0, PUPD=Disabled */
360        write_config_reg(CONTROL_PADCONF_DSS_D12, 0);
361        /* LCD_D13 pin configuration, PIN = R11, Mode = 0, PUPD=Disabled */
362        write_config_reg(CONTROL_PADCONF_DSS_D13, 0);
363        /* LCD_D14 pin configuration, PIN = V11, Mode = 0, PUPD=Disabled */
364        write_config_reg(CONTROL_PADCONF_DSS_D14, 0);
365        /* LCD_D15 pin configuration, PIN = W11, Mode = 0, PUPD=Disabled */
366        write_config_reg(CONTROL_PADCONF_DSS_D15, 0);
367        /* LCD_D16 pin configuration, PIN = P12, Mode = 0, PUPD=Disabled */
368        write_config_reg(CONTROL_PADCONF_DSS_D16, 0);
369        /* LCD_D17 pin configuration, PIN = R12, Mode = 0, PUPD=Disabled */
370        write_config_reg(CONTROL_PADCONF_DSS_D17, 0);
371        /* LCD_PCLK pin configuration, PIN = W6, Mode = 0, PUPD=Disabled */
372        write_config_reg(CONTROL_PADCONF_DSS_PCLK, 0);
373        /* LCD_VSYNC pin configuration, PIN = V7, Mode = 0, PUPD=Disabled */
374        write_config_reg(CONTROL_PADCONF_DSS_VSYNC, 0);
375        /* LCD_HSYNC pin configuration, PIN = Y6, Mode = 0, PUPD=Disabled */
376        write_config_reg(CONTROL_PADCONF_DSS_HSYNC, 0);
377        /* LCD_ACBIAS pin configuration, PIN = W7, Mode = 0, PUPD=Disabled */
378        write_config_reg(CONTROL_PADCONF_DSS_ACBIAS, 0);
379}
380
381/****************************************
382 * Routine: muxSetupMMCSD (ostboot)
383 * Description: set up MMC muxing
384 *****************************************/
385void muxSetupMMCSD(void)
386{
387        /* SDMMC_CLKI pin configuration,  PIN = H15, Mode = 0, PUPD=Disabled */
388        write_config_reg(CONTROL_PADCONF_MMC_CLKI, 0);
389        /* SDMMC_CLKO pin configuration,  PIN = G19, Mode = 0, PUPD=Disabled */
390        write_config_reg(CONTROL_PADCONF_MMC_CLKO, 0);
391        /* SDMMC_CMD pin configuration,   PIN = H18, Mode = 0, PUPD=Disabled */
392        write_config_reg(CONTROL_PADCONF_MMC_CMD, 0);
393        /* SDMMC_DAT0 pin configuration,  PIN = F20, Mode = 0, PUPD=Disabled */
394        write_config_reg(CONTROL_PADCONF_MMC_DAT0, 0);
395        /* SDMMC_DAT1 pin configuration,  PIN = H14, Mode = 0, PUPD=Disabled */
396        write_config_reg(CONTROL_PADCONF_MMC_DAT1, 0);
397        /* SDMMC_DAT2 pin configuration,  PIN = E19, Mode = 0, PUPD=Disabled */
398        write_config_reg(CONTROL_PADCONF_MMC_DAT2, 0);
399        /* SDMMC_DAT3 pin configuration,  PIN = D19, Mode = 0, PUPD=Disabled */
400        write_config_reg(CONTROL_PADCONF_MMC_DAT3, 0);
401        /* SDMMC_DDIR0 pin configuration, PIN = F19, Mode = 0, PUPD=Disabled */
402        write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR0, 0);
403        /* SDMMC_DDIR1 pin configuration, PIN = E20, Mode = 0, PUPD=Disabled */
404        write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR1, 0);
405        /* SDMMC_DDIR2 pin configuration, PIN = F18, Mode = 0, PUPD=Disabled */
406        write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR2, 0);
407        /* SDMMC_DDIR3 pin configuration, PIN = E18, Mode = 0, PUPD=Disabled */
408        write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR3, 0);
409        /* SDMMC_CDIR pin configuration,  PIN = G18, Mode = 0, PUPD=Disabled */
410        write_config_reg(CONTROL_PADCONF_MMC_CMD_DIR, 0);
411}
412
413/******************************************
414 * Routine: muxSetupTouchScreen (ostboot)
415 * Description:  Set up touch screen muxing
416 *******************************************/
417void muxSetupTouchScreen(void)
418{
419        /* SPI1_CLK pin configuration,  PIN = U18, Mode = 0, PUPD=Disabled */
420        write_config_reg(CONTROL_PADCONF_SPI1_CLK, 0);
421        /* SPI1_MOSI pin configuration, PIN = V20, Mode = 0, PUPD=Disabled */
422        write_config_reg(CONTROL_PADCONF_SPI1_SIMO, 0);
423        /* SPI1_MISO pin configuration, PIN = T18, Mode = 0, PUPD=Disabled */
424        write_config_reg(CONTROL_PADCONF_SPI1_SOMI, 0);
425        /* SPI1_nCS0 pin configuration, PIN = U19, Mode = 0, PUPD=Disabled */
426        write_config_reg(CONTROL_PADCONF_SPI1_NCS0, 0);
427#define CONTROL_PADCONF_GPIO85  CONTROL_PADCONF_SPI1_NCS1
428        /* PEN_IRQ pin configuration,   PIN = N15, Mode = 3, PUPD=Disabled */
429        write_config_reg(CONTROL_PADCONF_GPIO85, 3);
430}
431
432/***************************************************************
433 * Routine: muxSetupGPMC (ostboot)
434 * Description: Configures balls which cam up in protected mode
435 ***************************************************************/
436void muxSetupGPMC(void)
437{
438        /* gpmc_io_dir, MCR */
439        volatile unsigned int *MCR = (unsigned int *) 0x4800008C;
440        *MCR = 0x19000000;
441
442        /* NOR FLASH CS0 */
443        /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode 0; Byte-3 */
444        write_config_reg(CONTROL_PADCONF_GPMC_D2_BYTE3, 0);
445        /* MPDB(Multi Port Debug Port) CS1 */
446        /* signal - gpmc_ncs1; pin - N8; offset - 0x008D; mode 0; Byte-1 */
447        write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE1, 0);
448        /* signal - Gpmc_ncs2; pin - E2; offset - 0x008E; mode 0; Byte-2 */
449        write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE2, 0);
450        /* signal - Gpmc_ncs3; pin - N2; offset - 0x008F; mode 0; Byte-3 */
451        write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE3, 0);
452        /* signal - Gpmc_ncs4; pin - ??; offset - 0x0090; mode 0; Byte-4 */
453        write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE4, 0);
454        /* signal - Gpmc_ncs5; pin - ??; offset - 0x0091; mode 0; Byte-5 */
455        write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE5, 0);
456        /* signal - Gpmc_ncs6; pin - ??; offset - 0x0092; mode 0; Byte-6 */
457        write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE6, 0);
458        /* signal - Gpmc_ncs7; pin - ??; offset - 0x0093; mode 0; Byte-7 */
459        write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE7, 0);
460}
461
462/****************************************************************
463 * Routine: muxSetupSDRC  (ostboot)
464 * Description: Configures balls which come up in protected mode
465 ****************************************************************/
466void muxSetupSDRC(void)
467{
468        /* It's set by IPL */
469}
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