1 | /* |
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2 | * (C) Copyright 2005-2007 |
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3 | * Samsung Electronics, |
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4 | * Kyungmin Park <kyungmin.park@samsung.com> |
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5 | * |
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6 | * Derived from omap2420 |
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7 | * |
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8 | * This program is free software; you can redistribute it and/or |
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9 | * modify it under the terms of the GNU General Public License as |
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10 | * published by the Free Software Foundation; either version 2 of |
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11 | * the License, or (at your option) any later version. |
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12 | * |
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13 | * This program is distributed in the hope that it will be useful, |
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14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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16 | * GNU General Public License for more details. |
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17 | * |
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18 | * You should have received a copy of the GNU General Public License |
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19 | * along with this program; if not, write to the Free Software |
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20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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21 | * MA 02111-1307 USA |
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22 | */ |
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23 | |
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24 | #include <common.h> |
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25 | #include <asm/arch/omap2420.h> |
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26 | #include <asm/io.h> |
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27 | #include <asm/arch/bits.h> |
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28 | #include <asm/arch/mux.h> |
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29 | #include <asm/arch/mem.h> |
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30 | #include <asm/arch/clocks.h> |
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31 | #include <asm/arch/sys_proto.h> |
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32 | #include <asm/arch/sys_info.h> |
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33 | |
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34 | #include "mem.h" |
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35 | |
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36 | /************************************************************ |
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37 | * sdelay() - simple spin loop. Will be constant time as |
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38 | * its generally used in 12MHz bypass conditions only. This |
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39 | * is necessary until timers are accessible. |
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40 | * |
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41 | * not inline to increase chances its in cache when called |
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42 | *************************************************************/ |
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43 | void sdelay(unsigned long loops) |
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44 | { |
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45 | __asm__("1:\n" "subs %0, %1, #1\n" |
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46 | "bne 1b":"=r" (loops):"0"(loops)); |
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47 | } |
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48 | |
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49 | /******************************************************************** |
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50 | * prcm_init() - inits clocks for PRCM as defined in clocks.h |
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51 | * (config II default). |
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52 | * -- called from SRAM, or Flash (using temp SRAM stack). |
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53 | ********************************************************************/ |
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54 | void prcm_init(void) { } |
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55 | |
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56 | /************************************************************************** |
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57 | * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow |
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58 | * command line mem=xyz use all memory with out discontigious support |
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59 | * compiled in. Could do it at the ATAG, but there really is two banks... |
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60 | * Called as part of 2nd phase DDR init. |
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61 | **************************************************************************/ |
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62 | void make_cs1_contiguous(void) |
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63 | { |
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64 | u32 size, a_add_low, a_add_high; |
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65 | |
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66 | size = get_sdr_cs_size(SDRC_CS0_OSET); |
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67 | size /= SZ_32M; /* find size to offset CS1 */ |
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68 | a_add_high = (size & 3) << 8; /* set up low field */ |
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69 | a_add_low = (size & 0x3C) >> 2; /* set up high field */ |
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70 | __raw_writel((a_add_high | a_add_low), SDRC_CS_CFG); |
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71 | |
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72 | } |
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73 | |
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74 | /******************************************************** |
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75 | * mem_ok() - test used to see if timings are correct |
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76 | * for a part. Helps in gussing which part |
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77 | * we are currently using. |
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78 | *******************************************************/ |
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79 | u32 mem_ok(void) |
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80 | { |
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81 | u32 val1, val2; |
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82 | u32 pattern = 0x12345678; |
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83 | |
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84 | /* clear pos A */ |
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85 | __raw_writel(0x0, OMAP2420_SDRC_CS0 + 0x400); |
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86 | /* pattern to pos B */ |
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87 | __raw_writel(pattern, OMAP2420_SDRC_CS0); |
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88 | /* remove pattern off the bus */ |
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89 | __raw_writel(0x0, OMAP2420_SDRC_CS0 + 4); |
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90 | /* get pos A value */ |
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91 | val1 = __raw_readl(OMAP2420_SDRC_CS0 + 0x400); |
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92 | val2 = __raw_readl(OMAP2420_SDRC_CS0); /* get val2 */ |
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93 | |
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94 | /* see if pos A value changed */ |
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95 | if ((val1 != 0) || (val2 != pattern)) |
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96 | return (0); |
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97 | else |
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98 | return (1); |
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99 | } |
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100 | |
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101 | /******************************************************** |
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102 | * sdrc_init() - init the sdrc chip selects CS0 and CS1 |
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103 | * - early init routines, called from flash or |
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104 | * SRAM. |
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105 | *******************************************************/ |
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106 | void sdrc_init(void) |
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107 | { |
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108 | #define EARLY_INIT 1 |
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109 | /* only init up first bank here */ |
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110 | do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT); |
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111 | } |
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112 | |
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113 | /************************************************************************* |
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114 | * do_sdrc_init(): initialize the SDRAM for use. |
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115 | * -called from low level code with stack only. |
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116 | * -code sets up SDRAM timing and muxing for 2422 or 2420. |
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117 | * -optimal settings can be placed here, or redone after i2c |
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118 | * inspection of board info |
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119 | * |
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120 | * This is a bit ugly, but should handle all memory moduels |
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121 | * used with the APOLLON. The first time though this code from s_init() |
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122 | * we configure the first chip select. Later on we come back and |
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123 | * will configure the 2nd chip select if it exists. |
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124 | * |
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125 | **************************************************************************/ |
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126 | void do_sdrc_init(u32 offset, u32 early) |
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127 | { |
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128 | } |
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129 | |
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130 | /***************************************************** |
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131 | * gpmc_init(): init gpmc bus |
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132 | * Init GPMC for x16, MuxMode (SDRAM in x32). |
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133 | * This code can only be executed from SRAM or SDRAM. |
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134 | *****************************************************/ |
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135 | void gpmc_init(void) |
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136 | { |
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137 | u32 mux = 0, mtype, mwidth, rev, tval; |
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138 | |
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139 | rev = get_cpu_rev(); |
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140 | if (rev == CPU_2420_2422_ES1) |
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141 | tval = 1; |
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142 | else |
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143 | tval = 0; /* disable bit switched meaning */ |
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144 | |
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145 | /* global settings */ |
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146 | __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ |
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147 | __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ |
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148 | __raw_writel(tval, GPMC_TIMEOUT_CONTROL); /* timeout disable */ |
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149 | #ifdef CFG_NAND_BOOT |
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150 | /* set nWP, disable limited addr */ |
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151 | __raw_writel(0x001, GPMC_CONFIG); |
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152 | #else |
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153 | /* set nWP, disable limited addr */ |
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154 | __raw_writel(0x111, GPMC_CONFIG); |
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155 | #endif |
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156 | |
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157 | /* discover bus connection from sysboot */ |
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158 | if (is_gpmc_muxed() == GPMC_MUXED) |
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159 | mux = BIT9; |
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160 | mtype = get_gpmc0_type(); |
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161 | mwidth = get_gpmc0_width(); |
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162 | |
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163 | /* setup cs0 */ |
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164 | __raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */ |
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165 | sdelay(1000); |
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166 | |
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167 | #ifdef CFG_NOR_BOOT |
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168 | __raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_0); |
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169 | __raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_0); |
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170 | __raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_0); |
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171 | __raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_0); |
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172 | __raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_0); |
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173 | __raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_0); |
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174 | __raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_0); |
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175 | #else |
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176 | __raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth, |
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177 | GPMC_CONFIG1_0); |
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178 | __raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0); |
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179 | __raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0); |
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180 | __raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0); |
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181 | __raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0); |
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182 | __raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0); |
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183 | __raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0); |
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184 | #endif |
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185 | sdelay(2000); |
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186 | |
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187 | /* setup cs1 */ |
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188 | __raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */ |
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189 | sdelay(1000); |
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190 | |
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191 | __raw_writel(APOLLON_24XX_GPMC_CONFIG1_1, GPMC_CONFIG1_1); |
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192 | __raw_writel(APOLLON_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1); |
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193 | __raw_writel(APOLLON_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1); |
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194 | __raw_writel(APOLLON_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1); |
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195 | __raw_writel(APOLLON_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1); |
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196 | __raw_writel(APOLLON_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1); |
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197 | __raw_writel(APOLLON_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1); |
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198 | sdelay(2000); |
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199 | |
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200 | /* setup cs2 */ |
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201 | __raw_writel(0x0, GPMC_CONFIG7_2); /* disable current map */ |
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202 | sdelay(1000); |
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203 | __raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth, |
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204 | GPMC_CONFIG1_2); |
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205 | /* It's same as cs 0 */ |
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206 | __raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_2); |
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207 | __raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_2); |
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208 | __raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_2); |
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209 | __raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_2); |
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210 | __raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_2); |
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211 | #ifdef CFG_NOR_BOOT |
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212 | __raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_2); |
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213 | #else |
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214 | __raw_writel(APOLLON_24XX_GPMC_CONFIG7_2, GPMC_CONFIG7_2); |
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215 | #endif |
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216 | |
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217 | #ifndef CFG_NOR_BOOT |
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218 | /* setup cs3 */ |
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219 | __raw_writel(0, GPMC_CONFIG7_3); /* disable any mapping */ |
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220 | sdelay(1000); |
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221 | |
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222 | __raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_3); |
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223 | __raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_3); |
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224 | __raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_3); |
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225 | __raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_3); |
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226 | __raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_3); |
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227 | __raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_3); |
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228 | __raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_3); |
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229 | #endif |
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230 | |
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231 | #ifndef ASYNC_NOR |
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232 | __raw_writew(0xaa, (APOLLON_CS3_BASE + 0xaaa)); |
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233 | __raw_writew(0x55, (APOLLON_CS3_BASE + 0x554)); |
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234 | __raw_writew(0xc0, (APOLLON_CS3_BASE | SYNC_NOR_VALUE)); |
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235 | #endif |
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236 | sdelay(2000); |
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237 | } |
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