source: SVN/rincon/u-boot/board/bf537-stamp/nand.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 2 years ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 3.1 KB
Line 
1/*
2 * (C) Copyright 2006 Aubrey.Li, aubrey.li@analog.com
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <asm/io.h>
25
26#if defined(CONFIG_CMD_NAND)
27
28#include <nand.h>
29
30#define CONCAT(a,b,c,d) a ## b ## c ## d
31#define PORT(a,b)  CONCAT(pPORT,a,b,)
32
33#ifndef CONFIG_NAND_GPIO_PORT
34#define CONFIG_NAND_GPIO_PORT F
35#endif
36
37/*
38 * hardware specific access to control-lines
39 */
40static void bfin_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
41{
42        register struct nand_chip *this = mtd->priv;
43        u32 IO_ADDR_W = (u32) this->IO_ADDR_W;
44
45        if (ctrl & NAND_CTRL_CHANGE) {
46                if( ctrl & NAND_CLE )
47                        IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_CLE;
48                else
49                        IO_ADDR_W = CFG_NAND_BASE;
50                if( ctrl & NAND_ALE )
51                        IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_ALE;
52                else
53                        IO_ADDR_W = CFG_NAND_BASE;
54                this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
55        }
56        this->IO_ADDR_R = this->IO_ADDR_W;
57
58        /* Drain the writebuffer */
59        SSYNC();
60
61        if (cmd != NAND_CMD_NONE)
62                writeb(cmd, this->IO_ADDR_W);
63}
64
65int bfin_device_ready(struct mtd_info *mtd)
66{
67        int ret = (*PORT(CONFIG_NAND_GPIO_PORT, IO) & BFIN_NAND_READY) ? 1 : 0;
68        SSYNC();
69        return ret;
70}
71
72/*
73 * Board-specific NAND initialization. The following members of the
74 * argument are board-specific (per include/linux/mtd/nand.h):
75 * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
76 * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
77 * - cmd_ctrl: hardwarespecific function for accesing control-lines
78 * - dev_ready: hardwarespecific function for  accesing device ready/busy line
79 * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
80 *   only be provided if a hardware ECC is available
81 * - ecc.mode: mode of ecc, see defines
82 * - chip_delay: chip dependent delay for transfering data from array to
83 *   read regs (tR)
84 * - options: various chip options. They can partly be set to inform
85 *   nand_scan about special functionality. See the defines for further
86 *   explanation
87 * Members with a "?" were not set in the merged testing-NAND branch,
88 * so they are not set here either.
89 */
90void board_nand_init(struct nand_chip *nand)
91{
92        *PORT(CONFIG_NAND_GPIO_PORT, _FER) &= ~BFIN_NAND_READY;
93        *PORT(CONFIG_NAND_GPIO_PORT, IO_DIR) &= ~BFIN_NAND_READY;
94        *PORT(CONFIG_NAND_GPIO_PORT, IO_INEN) |= BFIN_NAND_READY;
95
96        nand->cmd_ctrl = bfin_hwcontrol;
97        nand->ecc.mode = NAND_ECC_SOFT;
98        nand->dev_ready = bfin_device_ready;
99        nand->chip_delay = 30;
100}
101#endif
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