source: SVN/rincon/u-boot/board/csb472/init.S @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 7.1 KB
Line 
1/******************************************************************************
2 *
3 *       This source code has been made available to you by IBM on an AS-IS
4 *       basis.  Anyone receiving this source is licensed under IBM
5 *       copyrights to use it in any way he or she deems fit, including
6 *       copying it, modifying it, compiling it, and redistributing it either
7 *       with or without modifications.  No license under IBM patents or
8 *       patent applications is to be implied by the copyright license.
9 *
10 *       Any user of this software should understand that IBM cannot provide
11 *       technical support for this software and will not be responsible for
12 *       any consequences resulting from the use of this software.
13 *
14 *       Any person who transfers this source code or any derivative work
15 *       must include the IBM copyright notice, this paragraph, and the
16 *       preceding two paragraphs in the transferred software.
17 *
18 *       COPYRIGHT   I B M   CORPORATION 1995
19 *       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
20 *
21 *****************************************************************************/
22#include <config.h>
23#include <ppc4xx.h>
24
25#define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
26
27#include <ppc_asm.tmpl>
28#include <ppc_defs.h>
29
30#include <asm/cache.h>
31#include <asm/mmu.h>
32
33#define LI32(reg,val) \
34        addis   reg,0,val@h;\
35        ori     reg,reg,val@l
36
37#define WDCR_EBC(reg,val) \
38        addi    r4,0,reg;\
39        mtdcr   ebccfga,r4;\
40        addis   r4,0,val@h;\
41        ori     r4,r4,val@l;\
42        mtdcr   ebccfgd,r4
43
44#define WDCR_SDRAM(reg,val) \
45        addi    r4,0,reg;\
46        mtdcr   memcfga,r4;\
47        addis   r4,0,val@h;\
48        ori     r4,r4,val@l;\
49        mtdcr   memcfgd,r4
50
51/******************************************************************************
52 * Function:    ext_bus_cntlr_init
53 *
54 * Description: Configures EBC Controller and a few basic chip selects.
55 *
56 *              CS0 is setup to get the Boot Flash out of the addresss range
57 *              so that we may setup a stack.  CS7 is setup so that we can
58 *              access and reset the hardware watchdog.
59 *
60 *              IMPORTANT: For pass1 this code must run from
61 *              cache since you can not reliably change a peripheral banks
62 *              timing register (pbxap) while running code from that bank.
63 *              For ex., since we are running from ROM on bank 0, we can NOT
64 *              execute the code that modifies bank 0 timings from ROM, so
65 *              we run it from cache.
66 *
67 * Notes:       Does NOT use the stack.
68 *****************************************************************************/
69        .section ".text"
70        .align  2
71        .globl  ext_bus_cntlr_init
72        .type   ext_bus_cntlr_init, @function
73ext_bus_cntlr_init:
74        mflr    r0
75        /********************************************************************
76         * Prefetch entire ext_bus_cntrl_init function into the icache.
77         * This is necessary because we are going to change the same CS we
78         * are executing from.  Otherwise a CPU lockup may occur.
79         *******************************************************************/
80        bl      ..getAddr
81..getAddr:
82        mflr    r3                      /* get address of ..getAddr */
83
84        /* Calculate number of cache lines for this function */
85        addi    r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2)
86        mtctr   r4
87..ebcloop:
88        icbt    r0, r3                  /* prefetch cache line for addr in r3*/
89        addi    r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */
90        bdnz    ..ebcloop               /* continue for $CTR cache lines */
91
92        /********************************************************************
93         * Delay to ensure all accesses to ROM are complete before changing
94         * bank 0 timings. 200usec should be enough.
95         * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
96         *******************************************************************/
97        addis   r3, 0, 0x0
98        ori     r3, r3, 0xA000          /* wait 200us from reset */
99        mtctr   r3
100..spinlp:
101        bdnz    ..spinlp                /* spin loop */
102
103        /********************************************************************
104         * SETUP CPC0_CR0
105         *******************************************************************/
106        LI32(r4, 0x00c01030)
107        mtdcr   cntrl0, r4
108
109        /********************************************************************
110         * Setup CPC0_CR1: Change PCIINT signal to PerWE
111         *******************************************************************/
112        mfdcr   r4, cntrl1
113        ori     r4, r4, 0x4000
114        mtdcr   cntrl1, r4
115
116        /********************************************************************
117         * Setup External Bus Controller (EBC).
118         *******************************************************************/
119        WDCR_EBC(epcr, 0xd84c0000)
120        /********************************************************************
121         * Memory Bank 0 (Intel 28F640J3 Flash) initialization
122         *******************************************************************/
123        /*WDCR_EBC(pb0ap, 0x03055200)*/
124        /*WDCR_EBC(pb0ap, 0x04055200)*/
125        WDCR_EBC(pb0ap, 0x08055200)
126        WDCR_EBC(pb0cr, 0xff87a000)
127        /********************************************************************
128         * Memory Bank 3 (Xilinx XC95144 CPLD) initialization
129         *******************************************************************/
130        /*WDCR_EBC(pb3ap, 0x07869200)*/
131        WDCR_EBC(pb3ap, 0x04055200)
132        WDCR_EBC(pb3cr, 0xf081c000)
133        /********************************************************************
134         * Memory Bank 1,2,4-7 (Unused) initialization
135         *******************************************************************/
136        WDCR_EBC(pb1ap, 0)
137        WDCR_EBC(pb1cr, 0)
138        WDCR_EBC(pb2ap, 0)
139        WDCR_EBC(pb2cr, 0)
140        WDCR_EBC(pb4ap, 0)
141        WDCR_EBC(pb4cr, 0)
142        WDCR_EBC(pb5ap, 0)
143        WDCR_EBC(pb5cr, 0)
144        WDCR_EBC(pb6ap, 0)
145        WDCR_EBC(pb6cr, 0)
146        WDCR_EBC(pb7ap, 0)
147        WDCR_EBC(pb7cr, 0)
148
149        /* We are all done */
150        mtlr    r0                      /* Restore link register */
151        blr                             /* Return to calling function */
152.Lfe0:  .size   ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
153/* end ext_bus_cntlr_init() */
154
155/******************************************************************************
156 * Function:    sdram_init
157 *
158 * Description: Configures SDRAM memory banks.
159 *
160 * Notes:       Does NOT use the stack.
161 *****************************************************************************/
162        .section ".text"
163        .align  2
164        .globl  sdram_init
165        .type   sdram_init, @function
166sdram_init:
167
168        /*
169         * Disable memory controller to allow
170         * values to be changed.
171         */
172        WDCR_SDRAM(mem_mcopt1, 0x00000000)
173
174        /*
175         * Configure Memory Banks
176         */
177        WDCR_SDRAM(mem_mb0cf, 0x00062001)
178        WDCR_SDRAM(mem_mb1cf, 0x00000000)
179        WDCR_SDRAM(mem_mb2cf, 0x00000000)
180        WDCR_SDRAM(mem_mb3cf, 0x00000000)
181
182        /*
183         * Set up SDTR1 (SDRAM Timing Register)
184         */
185        WDCR_SDRAM(mem_sdtr1, 0x00854009)
186
187        /*
188         * Set RTR (Refresh Timing Register)
189         */
190        WDCR_SDRAM(mem_rtr,   0x10000000)
191        /* WDCR_SDRAM(mem_rtr,   0x05f00000) */
192
193        /********************************************************************
194         * Delay to ensure 200usec have elapsed since reset. Assume worst
195         * case that the core is running 200Mhz:
196         *        200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
197         *******************************************************************/
198        addis   r3, 0, 0x0000
199        ori     r3, r3, 0xA000          /* Wait >200us from reset */
200        mtctr   r3
201..spinlp2:
202        bdnz    ..spinlp2               /* spin loop */
203
204        /********************************************************************
205         * Set memory controller options reg, MCOPT1.
206         *******************************************************************/
207        WDCR_SDRAM(mem_mcopt1,0x80800000)
208
209..sdri_done:
210        blr                             /* Return to calling function */
211.Lfe1:  .size   sdram_init,.Lfe1-sdram_init
212/* end sdram_init() */
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