1 | /* |
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2 | * (C) Copyright 2006 DENX Software Engineering |
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3 | * |
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4 | * See file CREDITS for list of people who contributed to this |
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5 | * project. |
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6 | * |
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7 | * This program is free software; you can redistribute it and/or |
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8 | * modify it under the terms of the GNU General Public License as |
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9 | * published by the Free Software Foundation; either version 2 of |
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10 | * the License, or (at your option) any later version. |
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11 | * |
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12 | * This program is distributed in the hope that it will be useful, |
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13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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15 | * GNU General Public License for more details. |
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16 | * |
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17 | * You should have received a copy of the GNU General Public License |
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18 | * along with this program; if not, write to the Free Software |
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19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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20 | * MA 02111-1307 USA |
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21 | */ |
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22 | |
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23 | #include <common.h> |
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24 | |
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25 | #if defined(CONFIG_CMD_NAND) |
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26 | #if !defined(CONFIG_NAND_LEGACY) |
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27 | |
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28 | #include <nand.h> |
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29 | #include <asm/arch/pxa-regs.h> |
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30 | |
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31 | #ifdef CFG_DFC_DEBUG1 |
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32 | # define DFC_DEBUG1(fmt, args...) printf(fmt, ##args) |
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33 | #else |
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34 | # define DFC_DEBUG1(fmt, args...) |
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35 | #endif |
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36 | |
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37 | #ifdef CFG_DFC_DEBUG2 |
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38 | # define DFC_DEBUG2(fmt, args...) printf(fmt, ##args) |
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39 | #else |
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40 | # define DFC_DEBUG2(fmt, args...) |
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41 | #endif |
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42 | |
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43 | #ifdef CFG_DFC_DEBUG3 |
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44 | # define DFC_DEBUG3(fmt, args...) printf(fmt, ##args) |
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45 | #else |
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46 | # define DFC_DEBUG3(fmt, args...) |
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47 | #endif |
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48 | |
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49 | #define MIN(x, y) ((x < y) ? x : y) |
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50 | |
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51 | /* These really don't belong here, as they are specific to the NAND Model */ |
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52 | static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; |
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53 | |
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54 | static struct nand_bbt_descr delta_bbt_descr = { |
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55 | .options = 0, |
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56 | .offs = 0, |
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57 | .len = 2, |
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58 | .pattern = scan_ff_pattern |
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59 | }; |
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60 | |
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61 | static struct nand_ecclayout delta_oob = { |
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62 | .eccbytes = 6, |
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63 | .eccpos = {2, 3, 4, 5, 6, 7}, |
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64 | .oobfree = { {8, 2}, {12, 4} } |
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65 | }; |
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66 | |
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67 | /* |
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68 | * not required for Monahans DFC |
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69 | */ |
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70 | static void dfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
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71 | { |
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72 | return; |
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73 | } |
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74 | |
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75 | #if 0 |
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76 | /* read device ready pin */ |
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77 | static int dfc_device_ready(struct mtd_info *mtdinfo) |
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78 | { |
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79 | if(NDSR & NDSR_RDY) |
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80 | return 1; |
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81 | else |
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82 | return 0; |
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83 | return 0; |
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84 | } |
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85 | #endif |
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86 | |
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87 | /* |
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88 | * Write buf to the DFC Controller Data Buffer |
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89 | */ |
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90 | static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len) |
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91 | { |
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92 | unsigned long bytes_multi = len & 0xfffffffc; |
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93 | unsigned long rest = len & 0x3; |
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94 | unsigned long *long_buf; |
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95 | int i; |
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96 | |
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97 | DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf)); |
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98 | if(bytes_multi) { |
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99 | for(i=0; i<bytes_multi; i+=4) { |
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100 | long_buf = (unsigned long*) &buf[i]; |
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101 | NDDB = *long_buf; |
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102 | } |
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103 | } |
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104 | if(rest) { |
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105 | printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n"); |
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106 | } |
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107 | return; |
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108 | } |
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109 | |
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110 | |
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111 | static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len) |
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112 | { |
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113 | int i=0, j; |
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114 | |
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115 | /* we have to be carefull not to overflow the buffer if len is |
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116 | * not a multiple of 4 */ |
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117 | unsigned long bytes_multi = len & 0xfffffffc; |
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118 | unsigned long rest = len & 0x3; |
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119 | unsigned long *long_buf; |
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120 | |
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121 | DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len); |
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122 | /* if there are any, first copy multiple of 4 bytes */ |
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123 | if(bytes_multi) { |
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124 | for(i=0; i<bytes_multi; i+=4) { |
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125 | long_buf = (unsigned long*) &buf[i]; |
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126 | *long_buf = NDDB; |
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127 | } |
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128 | } |
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129 | |
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130 | /* ...then the rest */ |
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131 | if(rest) { |
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132 | unsigned long rest_data = NDDB; |
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133 | for(j=0;j<rest; j++) |
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134 | buf[i+j] = (u_char) ((rest_data>>j) & 0xff); |
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135 | } |
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136 | |
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137 | return; |
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138 | } |
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139 | |
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140 | /* |
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141 | * read a word. Not implemented as not used in NAND code. |
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142 | */ |
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143 | static u16 dfc_read_word(struct mtd_info *mtd) |
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144 | { |
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145 | printf("dfc_read_word: UNIMPLEMENTED.\n"); |
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146 | return 0; |
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147 | } |
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148 | |
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149 | /* global var, too bad: mk@tbd: move to ->priv pointer */ |
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150 | static unsigned long read_buf = 0; |
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151 | static int bytes_read = -1; |
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152 | |
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153 | /* |
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154 | * read a byte from NDDB Because we can only read 4 bytes from NDDB at |
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155 | * a time, we buffer the remaining bytes. The buffer is reset when a |
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156 | * new command is sent to the chip. |
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157 | * |
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158 | * WARNING: |
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159 | * This function is currently only used to read status and id |
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160 | * bytes. For these commands always 8 bytes need to be read from |
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161 | * NDDB. So we read and discard these bytes right now. In case this |
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162 | * function is used for anything else in the future, we must check |
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163 | * what was the last command issued and read the appropriate amount of |
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164 | * bytes respectively. |
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165 | */ |
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166 | static u_char dfc_read_byte(struct mtd_info *mtd) |
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167 | { |
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168 | unsigned char byte; |
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169 | unsigned long dummy; |
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170 | |
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171 | if(bytes_read < 0) { |
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172 | read_buf = NDDB; |
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173 | dummy = NDDB; |
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174 | bytes_read = 0; |
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175 | } |
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176 | byte = (unsigned char) (read_buf>>(8 * bytes_read++)); |
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177 | if(bytes_read >= 4) |
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178 | bytes_read = -1; |
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179 | |
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180 | DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf); |
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181 | return byte; |
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182 | } |
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183 | |
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184 | /* calculate delta between OSCR values start and now */ |
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185 | static unsigned long get_delta(unsigned long start) |
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186 | { |
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187 | unsigned long cur = OSCR; |
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188 | |
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189 | if(cur < start) /* OSCR overflowed */ |
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190 | return (cur + (start^0xffffffff)); |
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191 | else |
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192 | return (cur - start); |
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193 | } |
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194 | |
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195 | /* delay function, this doesn't belong here */ |
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196 | static void wait_us(unsigned long us) |
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197 | { |
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198 | unsigned long start = OSCR; |
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199 | us *= OSCR_CLK_FREQ; |
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200 | |
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201 | while (get_delta(start) < us) { |
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202 | /* do nothing */ |
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203 | } |
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204 | } |
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205 | |
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206 | static void dfc_clear_nddb(void) |
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207 | { |
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208 | NDCR &= ~NDCR_ND_RUN; |
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209 | wait_us(CFG_NAND_OTHER_TO); |
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210 | } |
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211 | |
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212 | /* wait_event with timeout */ |
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213 | static unsigned long dfc_wait_event(unsigned long event) |
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214 | { |
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215 | unsigned long ndsr, timeout, start = OSCR; |
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216 | |
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217 | if(!event) |
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218 | return 0xff000000; |
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219 | else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD)) |
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220 | timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ; |
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221 | else |
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222 | timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ; |
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223 | |
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224 | while(1) { |
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225 | ndsr = NDSR; |
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226 | if(ndsr & event) { |
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227 | NDSR |= event; |
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228 | break; |
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229 | } |
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230 | if(get_delta(start) > timeout) { |
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231 | DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event); |
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232 | return 0xff000000; |
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233 | } |
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234 | |
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235 | } |
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236 | return ndsr; |
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237 | } |
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238 | |
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239 | /* we don't always wan't to do this */ |
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240 | static void dfc_new_cmd(void) |
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241 | { |
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242 | int retry = 0; |
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243 | unsigned long status; |
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244 | |
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245 | while(retry++ <= CFG_NAND_SENDCMD_RETRY) { |
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246 | /* Clear NDSR */ |
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247 | NDSR = 0xFFF; |
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248 | |
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249 | /* set NDCR[NDRUN] */ |
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250 | if(!(NDCR & NDCR_ND_RUN)) |
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251 | NDCR |= NDCR_ND_RUN; |
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252 | |
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253 | status = dfc_wait_event(NDSR_WRCMDREQ); |
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254 | |
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255 | if(status & NDSR_WRCMDREQ) |
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256 | return; |
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257 | |
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258 | DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry); |
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259 | dfc_clear_nddb(); |
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260 | } |
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261 | DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry); |
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262 | } |
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263 | |
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264 | /* this function is called after Programm and Erase Operations to |
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265 | * check for success or failure */ |
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266 | static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this) |
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267 | { |
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268 | unsigned long ndsr=0, event=0; |
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269 | int state = this->state; |
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270 | |
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271 | if(state == FL_WRITING) { |
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272 | event = NDSR_CS0_CMDD | NDSR_CS0_BBD; |
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273 | } else if(state == FL_ERASING) { |
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274 | event = NDSR_CS0_CMDD | NDSR_CS0_BBD; |
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275 | } |
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276 | |
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277 | ndsr = dfc_wait_event(event); |
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278 | |
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279 | if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000)) |
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280 | return(0x1); /* Status Read error */ |
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281 | return 0; |
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282 | } |
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283 | |
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284 | /* cmdfunc send commands to the DFC */ |
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285 | static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command, |
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286 | int column, int page_addr) |
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287 | { |
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288 | /* register struct nand_chip *this = mtd->priv; */ |
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289 | unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0; |
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290 | |
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291 | /* clear the ugly byte read buffer */ |
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292 | bytes_read = -1; |
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293 | read_buf = 0; |
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294 | |
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295 | switch (command) { |
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296 | case NAND_CMD_READ0: |
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297 | DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1)); |
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298 | dfc_new_cmd(); |
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299 | ndcb0 = (NAND_CMD_READ0 | (4<<16)); |
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300 | column >>= 1; /* adjust for 16 bit bus */ |
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301 | ndcb1 = (((column>>1) & 0xff) | |
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302 | ((page_addr<<8) & 0xff00) | |
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303 | ((page_addr<<8) & 0xff0000) | |
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304 | ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */ |
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305 | event = NDSR_RDDREQ; |
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306 | goto write_cmd; |
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307 | case NAND_CMD_READ1: |
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308 | DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n"); |
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309 | goto end; |
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310 | case NAND_CMD_READOOB: |
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311 | DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n"); |
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312 | goto end; |
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313 | case NAND_CMD_READID: |
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314 | dfc_new_cmd(); |
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315 | DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n"); |
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316 | ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/ |
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317 | event = NDSR_RDDREQ; |
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318 | goto write_cmd; |
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319 | case NAND_CMD_PAGEPROG: |
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320 | /* sent as a multicommand in NAND_CMD_SEQIN */ |
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321 | DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n"); |
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322 | goto end; |
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323 | case NAND_CMD_ERASE1: |
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324 | DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1)); |
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325 | dfc_new_cmd(); |
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326 | ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16)); |
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327 | ndcb1 = (page_addr & 0x00ffffff); |
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328 | goto write_cmd; |
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329 | case NAND_CMD_ERASE2: |
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330 | DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n"); |
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331 | goto end; |
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332 | case NAND_CMD_SEQIN: |
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333 | /* send PAGE_PROG command(0x1080) */ |
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334 | dfc_new_cmd(); |
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335 | DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1)); |
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336 | ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16)); |
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337 | column >>= 1; /* adjust for 16 bit bus */ |
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338 | ndcb1 = (((column>>1) & 0xff) | |
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339 | ((page_addr<<8) & 0xff00) | |
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340 | ((page_addr<<8) & 0xff0000) | |
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341 | ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */ |
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342 | event = NDSR_WRDREQ; |
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343 | goto write_cmd; |
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344 | case NAND_CMD_STATUS: |
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345 | DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n"); |
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346 | dfc_new_cmd(); |
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347 | ndcb0 = NAND_CMD_STATUS | (4<<21); |
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348 | event = NDSR_RDDREQ; |
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349 | goto write_cmd; |
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350 | case NAND_CMD_RESET: |
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351 | DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n"); |
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352 | ndcb0 = NAND_CMD_RESET | (5<<21); |
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353 | event = NDSR_CS0_CMDD; |
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354 | goto write_cmd; |
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355 | default: |
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356 | printk("dfc_cmdfunc: error, unsupported command.\n"); |
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357 | goto end; |
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358 | } |
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359 | |
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360 | write_cmd: |
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361 | NDCB0 = ndcb0; |
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362 | NDCB0 = ndcb1; |
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363 | NDCB0 = ndcb2; |
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364 | |
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365 | /* wait_event: */ |
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366 | dfc_wait_event(event); |
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367 | end: |
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368 | return; |
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369 | } |
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370 | |
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371 | static void dfc_gpio_init(void) |
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372 | { |
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373 | DFC_DEBUG2("Setting up DFC GPIO's.\n"); |
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374 | |
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375 | /* no idea what is done here, see zylonite.c */ |
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376 | GPIO4 = 0x1; |
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377 | |
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378 | DF_ALE_WE1 = 0x00000001; |
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379 | DF_ALE_WE2 = 0x00000001; |
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380 | DF_nCS0 = 0x00000001; |
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381 | DF_nCS1 = 0x00000001; |
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382 | DF_nWE = 0x00000001; |
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383 | DF_nRE = 0x00000001; |
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384 | DF_IO0 = 0x00000001; |
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385 | DF_IO8 = 0x00000001; |
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386 | DF_IO1 = 0x00000001; |
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387 | DF_IO9 = 0x00000001; |
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388 | DF_IO2 = 0x00000001; |
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389 | DF_IO10 = 0x00000001; |
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390 | DF_IO3 = 0x00000001; |
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391 | DF_IO11 = 0x00000001; |
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392 | DF_IO4 = 0x00000001; |
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393 | DF_IO12 = 0x00000001; |
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394 | DF_IO5 = 0x00000001; |
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395 | DF_IO13 = 0x00000001; |
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396 | DF_IO6 = 0x00000001; |
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397 | DF_IO14 = 0x00000001; |
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398 | DF_IO7 = 0x00000001; |
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399 | DF_IO15 = 0x00000001; |
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400 | |
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401 | DF_nWE = 0x1901; |
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402 | DF_nRE = 0x1901; |
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403 | DF_CLE_NOE = 0x1900; |
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404 | DF_ALE_WE1 = 0x1901; |
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405 | DF_INT_RnB = 0x1900; |
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406 | } |
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407 | |
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408 | /* |
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409 | * Board-specific NAND initialization. The following members of the |
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410 | * argument are board-specific (per include/linux/mtd/nand_new.h): |
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411 | * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device |
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412 | * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device |
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413 | * - hwcontrol: hardwarespecific function for accesing control-lines |
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414 | * - dev_ready: hardwarespecific function for accesing device ready/busy line |
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415 | * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must |
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416 | * only be provided if a hardware ECC is available |
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417 | * - ecc.mode: mode of ecc, see defines |
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418 | * - chip_delay: chip dependent delay for transfering data from array to |
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419 | * read regs (tR) |
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420 | * - options: various chip options. They can partly be set to inform |
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421 | * nand_scan about special functionality. See the defines for further |
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422 | * explanation |
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423 | * Members with a "?" were not set in the merged testing-NAND branch, |
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424 | * so they are not set here either. |
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425 | */ |
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426 | int board_nand_init(struct nand_chip *nand) |
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427 | { |
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428 | unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR; |
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429 | |
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430 | /* set up GPIO Control Registers */ |
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431 | dfc_gpio_init(); |
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432 | |
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433 | /* turn on the NAND Controller Clock (104 MHz @ D0) */ |
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434 | CKENA |= (CKENA_4_NAND | CKENA_9_SMC); |
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435 | |
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436 | #undef CFG_TIMING_TIGHT |
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437 | #ifndef CFG_TIMING_TIGHT |
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438 | tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1), |
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439 | DFC_MAX_tCH); |
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440 | tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1), |
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441 | DFC_MAX_tCS); |
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442 | tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1), |
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443 | DFC_MAX_tWH); |
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444 | tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1), |
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445 | DFC_MAX_tWP); |
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446 | tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1), |
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447 | DFC_MAX_tRH); |
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448 | tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1), |
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449 | DFC_MAX_tRP); |
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450 | tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1), |
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451 | DFC_MAX_tR); |
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452 | tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1), |
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453 | DFC_MAX_tWHR); |
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454 | tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1), |
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455 | DFC_MAX_tAR); |
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456 | #else /* this is the tight timing */ |
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457 | |
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458 | tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)), |
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459 | DFC_MAX_tCH); |
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460 | tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)), |
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461 | DFC_MAX_tCS); |
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462 | tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)), |
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463 | DFC_MAX_tWH); |
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464 | tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)), |
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465 | DFC_MAX_tWP); |
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466 | tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)), |
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467 | DFC_MAX_tRH); |
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468 | tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)), |
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469 | DFC_MAX_tRP); |
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470 | tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2), |
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471 | DFC_MAX_tR); |
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472 | tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2), |
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473 | DFC_MAX_tWHR); |
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474 | tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2), |
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475 | DFC_MAX_tAR); |
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476 | #endif /* CFG_TIMING_TIGHT */ |
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477 | |
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478 | |
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479 | DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR); |
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480 | |
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481 | /* tRP value is split in the register */ |
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482 | if(tRP & (1 << 4)) { |
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483 | tRP_high = 1; |
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484 | tRP &= ~(1 << 4); |
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485 | } else { |
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486 | tRP_high = 0; |
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487 | } |
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488 | |
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489 | NDTR0CS0 = (tCH << 19) | |
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490 | (tCS << 16) | |
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491 | (tWH << 11) | |
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492 | (tWP << 8) | |
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493 | (tRP_high << 6) | |
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494 | (tRH << 3) | |
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495 | (tRP << 0); |
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496 | |
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497 | NDTR1CS0 = (tR << 16) | |
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498 | (tWHR << 4) | |
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499 | (tAR << 0); |
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500 | |
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501 | /* If it doesn't work (unlikely) think about: |
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502 | * - ecc enable |
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503 | * - chip select don't care |
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504 | * - read id byte count |
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505 | * |
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506 | * Intentionally enabled by not setting bits: |
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507 | * - dma (DMA_EN) |
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508 | * - page size = 512 |
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509 | * - cs don't care, see if we can enable later! |
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510 | * - row address start position (after second cycle) |
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511 | * - pages per block = 32 |
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512 | * - ND_RDY : clears command buffer |
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513 | */ |
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514 | /* NDCR_NCSX | /\* Chip select busy don't care *\/ */ |
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515 | |
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516 | NDCR = (NDCR_SPARE_EN | /* use the spare area */ |
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517 | NDCR_DWIDTH_C | /* 16bit DFC data bus width */ |
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518 | NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */ |
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519 | (2 << 16) | /* read id count = 7 ???? mk@tbd */ |
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520 | NDCR_ND_ARB_EN | /* enable bus arbiter */ |
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521 | NDCR_RDYM | /* flash device ready ir masked */ |
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522 | NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */ |
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523 | NDCR_CS1_PAGEDM | |
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524 | NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */ |
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525 | NDCR_CS1_CMDDM | |
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526 | NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */ |
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527 | NDCR_CS1_BBDM | |
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528 | NDCR_DBERRM | /* double bit error ir masked */ |
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529 | NDCR_SBERRM | /* single bit error ir masked */ |
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530 | NDCR_WRDREQM | /* write data request ir masked */ |
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531 | NDCR_RDDREQM | /* read data request ir masked */ |
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532 | NDCR_WRCMDREQM); /* write command request ir masked */ |
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533 | |
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534 | |
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535 | /* wait 10 us due to cmd buffer clear reset */ |
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536 | /* wait(10); */ |
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537 | |
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538 | |
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539 | nand->cmd_ctrl = dfc_hwcontrol; |
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540 | /* nand->dev_ready = dfc_device_ready; */ |
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541 | nand->ecc.mode = NAND_ECC_SOFT; |
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542 | nand->ecc.layout = &delta_oob; |
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543 | nand->options = NAND_BUSWIDTH_16; |
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544 | nand->waitfunc = dfc_wait; |
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545 | nand->read_byte = dfc_read_byte; |
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546 | nand->read_word = dfc_read_word; |
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547 | nand->read_buf = dfc_read_buf; |
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548 | nand->write_buf = dfc_write_buf; |
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549 | |
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550 | nand->cmdfunc = dfc_cmdfunc; |
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551 | nand->badblock_pattern = &delta_bbt_descr; |
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552 | return 0; |
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553 | } |
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554 | |
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555 | #else |
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556 | #error "U-Boot legacy NAND support not available for Monahans DFC." |
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557 | #endif |
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558 | #endif |
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