source: SVN/rincon/u-boot/board/ep88x/ep88x.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 2 years ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 3.8 KB
Line 
1/*
2 * Copyright (C) 2005 Arabella Software Ltd.
3 * Yuli Barcohen <yuli@arabellasw.com>
4 *
5 * Support for Embedded Planet EP88x boards.
6 * Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <mpc8xx.h>
29
30/*
31 * SDRAM uses two Micron chips.
32 * Minimal CPU frequency is 40MHz.
33 */
34static uint sdram_table[] = {
35        /* Single read  (offset 0x00 in UPM RAM) */
36        0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x01B98404,
37        0x1FF74C00, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
38
39        /* Burst read   (offset 0x08 in UPM RAM) */
40        0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x00BDC404,
41        0x00FFCC00, 0x00FFCC00, 0x01FB8C00, 0x1FF74C00,
42        0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
43        0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
44
45        /* Single write (offset 0x18 in UPM RAM) */
46        0xEFCBCC04, 0x0F37C804, 0x0EEE8002, 0x01B90404,
47        0x1FF74C05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
48
49        /* Burst write  (offset 0x20 in UPM RAM) */
50        0xEFCBCC04, 0x0F37C804, 0x0EEE8000, 0x00BD4400,
51        0x00FFCC00, 0x00FFCC02, 0x01FB8C04, 0x1FF74C05,
52        0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
53        0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
54
55        /* Refresh      (offset 0x30 in UPM RAM) */
56        0xEFFACC04, 0x0FF5CC04, 0x0FFFCC04, 0x1FFFCC04,
57        0xFFFFCC05, 0xFFFFCC05, 0xEFFB8C34, 0x0FF74C34,
58        0x0FFACCB4, 0x0FF5CC34, 0x0FFFC034, 0x0FFFC0B4,
59
60        /* Exception    (offset 0x3C in UPM RAM) */
61        0x0FEA8034, 0x1FB54034, 0xFFFFCC34, 0xFFFFCC05
62};
63
64int board_early_init_f (void)
65{
66        vu_char *bcsr = (vu_char *)CFG_BCSR;
67
68        bcsr[0] |= 0x0C; /* Turn the LEDs off */
69        bcsr[2] |= 0x08; /* Enable flash WE# line - necessary for
70                            flash detection by CFI driver
71                         */
72
73#if defined(CONFIG_8xx_CONS_SMC1)
74        bcsr[6] |= 0x10; /* Enables RS-232 transceiver */
75#endif
76#if defined(CONFIG_8xx_CONS_SCC2)
77        bcsr[7] |= 0x10; /* Enables RS-232 transceiver */
78#endif
79#ifdef CONFIG_ETHER_ON_FEC1
80        bcsr[8] |= 0xC0; /* Enable Ethernet 1 PHY */
81#endif
82#ifdef CONFIG_ETHER_ON_FEC2
83        bcsr[8] |= 0x30; /* Enable Ethernet 2 PHY */
84#endif
85
86        return 0;
87}
88
89phys_size_t initdram (int board_type)
90{
91        long int msize;
92        volatile immap_t     *immap  = (volatile immap_t *)CFG_IMMR;
93        volatile memctl8xx_t *memctl = &immap->im_memctl;
94
95        upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
96
97        /* Configure SDRAM refresh */
98        memctl->memc_mptpr = MPTPR_PTP_DIV2; /* BRGCLK/2 */
99
100        memctl->memc_mamr = (65 << 24) | CFG_MAMR; /* No refresh */
101        udelay(100);
102
103        /* Run MRS pattern from location 0x36 */
104        memctl->memc_mar = 0x88;
105        memctl->memc_mcr = 0x80002236;
106        udelay(100);
107
108        memctl->memc_mamr |=  MAMR_PTAE; /* Enable refresh */
109        memctl->memc_or1   = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
110        memctl->memc_br1   =  CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
111
112        msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE);
113        memctl->memc_or1  |= ~(msize - 1);
114
115        return msize;
116}
117
118int checkboard( void )
119{
120        vu_char *bcsr = (vu_char *)CFG_BCSR;
121
122        puts("Board: ");
123        switch (bcsr[15]) {
124        case 0xE7:
125                puts("EP88xC 1.0");
126                break;
127        default:
128                printf("unknown ID=%02X", bcsr[15]);
129        }
130        printf("  CPLD revision %d\n", bcsr[14]);
131
132        return 0;
133}
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