source: SVN/rincon/u-boot/board/eric/init.S @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 12.0 KB
Line 
1/*------------------------------------------------------------------------------+ */
2/* */
3/*       This source code has been made available to you by IBM on an AS-IS */
4/*       basis.  Anyone receiving this source is licensed under IBM */
5/*       copyrights to use it in any way he or she deems fit, including */
6/*       copying it, modifying it, compiling it, and redistributing it either */
7/*       with or without modifications.  No license under IBM patents or */
8/*       patent applications is to be implied by the copyright license. */
9/* */
10/*       Any user of this software should understand that IBM cannot provide */
11/*       technical support for this software and will not be responsible for */
12/*       any consequences resulting from the use of this software. */
13/* */
14/*       Any person who transfers this source code or any derivative work */
15/*       must include the IBM copyright notice, this paragraph, and the */
16/*       preceding two paragraphs in the transferred software. */
17/* */
18/*       COPYRIGHT   I B M   CORPORATION 1995 */
19/*       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M */
20/*------------------------------------------------------------------------------- */
21
22/*----------------------------------------------------------------------------- */
23/* Function:     ext_bus_cntlr_init */
24/* Description:  Initializes the External Bus Controller for the external */
25/*              peripherals. IMPORTANT: For pass1 this code must run from */
26/*              cache since you can not reliably change a peripheral banks */
27/*              timing register (pbxap) while running code from that bank. */
28/*              For ex., since we are running from ROM on bank 0, we can NOT */
29/*              execute the code that modifies bank 0 timings from ROM, so */
30/*              we run it from cache. */
31/* */
32/*----------------------------------------------------------------------------- */
33#include <config.h>
34#include <ppc4xx.h>
35
36#define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
37
38#include <ppc_asm.tmpl>
39#include <ppc_defs.h>
40
41#include <asm/cache.h>
42#include <asm/mmu.h>
43
44
45        .globl  ext_bus_cntlr_init
46ext_bus_cntlr_init:
47        mflr    r4                      /* save link register */
48        bl      ..getAddr
49..getAddr:
50        mflr    r3                      /* get address of ..getAddr */
51        mtlr    r4                      /* restore link register */
52        addi    r4,0,14                 /* set ctr to 10; used to prefetch */
53        mtctr   r4                      /* 10 cache lines to fit this function */
54                                        /* in cache (gives us 8x10=80 instrctns) */
55..ebcloop:
56        icbt    r0,r3                   /* prefetch cache line for addr in r3 */
57        addi    r3,r3,32                /* move to next cache line */
58        bdnz    ..ebcloop               /* continue for 10 cache lines */
59
60        /*------------------------------------------------------------------- */
61        /* Delay to ensure all accesses to ROM are complete before changing */
62        /* bank 0 timings. 200usec should be enough. */
63        /*   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
64        /*------------------------------------------------------------------- */
65        addis   r3,0,0x0
66        ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
67        mtctr   r3
68..spinlp:
69        bdnz    ..spinlp                /* spin loop */
70
71        /*----------------------------------------------------------------------- */
72        /* Memory Bank 0 (Flash) initialization (from openbios) */
73        /*----------------------------------------------------------------------- */
74
75        addi    r4,0,pb0ap
76        mtdcr   ebccfga,r4
77        addis   r4,0,CS0_AP@h
78        ori     r4,r4,CS0_AP@l
79        mtdcr   ebccfgd,r4
80
81        addi    r4,0,pb0cr
82        mtdcr   ebccfga,r4
83        addis   r4,0,CS0_CR@h
84        ori     r4,r4,CS0_CR@l
85        mtdcr   ebccfgd,r4
86
87        /*----------------------------------------------------------------------- */
88        /* Memory Bank 1 (NVRAM/RTC) initialization */
89        /*----------------------------------------------------------------------- */
90
91        addi    r4,0,pb1ap
92        mtdcr   ebccfga,r4
93        addis   r4,0,CS1_AP@h
94        ori     r4,r4,CS1_AP@l
95        mtdcr   ebccfgd,r4
96
97        addi    r4,0,pb1cr
98        mtdcr   ebccfga,r4
99        addis   r4,0,CS1_CR@h
100        ori     r4,r4,CS1_CR@l
101        mtdcr   ebccfgd,r4
102
103        /*----------------------------------------------------------------------- */
104        /* Memory Bank 2 (A/D converter) initialization */
105        /*----------------------------------------------------------------------- */
106
107        addi    r4,0,pb2ap
108        mtdcr   ebccfga,r4
109        addis   r4,0,CS2_AP@h
110        ori     r4,r4,CS2_AP@l
111        mtdcr   ebccfgd,r4
112
113        addi    r4,0,pb2cr
114        mtdcr   ebccfga,r4
115        addis   r4,0,CS2_CR@h
116        ori     r4,r4,CS2_CR@l
117        mtdcr   ebccfgd,r4
118
119        /*----------------------------------------------------------------------- */
120        /* Memory Bank 3 (Ethernet PHY Reset) initialization */
121        /*----------------------------------------------------------------------- */
122
123        addi    r4,0,pb3ap
124        mtdcr   ebccfga,r4
125        addis   r4,0,CS3_AP@h
126        ori     r4,r4,CS3_AP@l
127        mtdcr   ebccfgd,r4
128
129        addi    r4,0,pb3cr
130        mtdcr   ebccfga,r4
131        addis   r4,0,CS3_CR@h
132        ori     r4,r4,CS3_CR@l
133        mtdcr   ebccfgd,r4
134
135        /*----------------------------------------------------------------------- */
136        /* Memory Bank 4 (PC-MIP PRSNT1#) initialization */
137        /*----------------------------------------------------------------------- */
138
139        addi    r4,0,pb4ap
140        mtdcr   ebccfga,r4
141        addis   r4,0,CS4_AP@h
142        ori     r4,r4,CS4_AP@l
143        mtdcr   ebccfgd,r4
144
145        addi    r4,0,pb4cr
146        mtdcr   ebccfga,r4
147        addis   r4,0,CS4_CR@h
148        ori     r4,r4,CS4_CR@l
149        mtdcr   ebccfgd,r4
150
151        /*----------------------------------------------------------------------- */
152        /* Memory Bank 5 (PC-MIP PRSNT2#) initialization */
153        /*----------------------------------------------------------------------- */
154
155        addi    r4,0,pb5ap
156        mtdcr   ebccfga,r4
157        addis   r4,0,CS5_AP@h
158        ori     r4,r4,CS5_AP@l
159        mtdcr   ebccfgd,r4
160
161        addi    r4,0,pb5cr
162        mtdcr   ebccfga,r4
163        addis   r4,0,CS5_CR@h
164        ori     r4,r4,CS5_CR@l
165        mtdcr   ebccfgd,r4
166
167        /*----------------------------------------------------------------------- */
168        /* Memory Bank 6 (CPU LED0) initialization */
169        /*----------------------------------------------------------------------- */
170
171        addi    r4,0,pb6ap
172        mtdcr   ebccfga,r4
173        addis   r4,0,CS6_AP@h
174        ori     r4,r4,CS6_AP@l
175        mtdcr   ebccfgd,r4
176
177        addi    r4,0,pb6cr
178        mtdcr   ebccfga,r4
179        addis   r4,0,CS6_CR@h
180        ori     r4,r4,CS5_CR@l
181        mtdcr   ebccfgd,r4
182
183        /*----------------------------------------------------------------------- */
184        /* Memory Bank 7 (CPU LED1) initialization */
185        /*----------------------------------------------------------------------- */
186
187        addi    r4,0,pb7ap
188        mtdcr   ebccfga,r4
189        addis   r4,0,CS7_AP@h
190        ori     r4,r4,CS7_AP@l
191        mtdcr   ebccfgd,r4
192
193        addi    r4,0,pb7cr
194        mtdcr   ebccfga,r4
195        addis   r4,0,CS7_CR@h
196        ori     r4,r4,CS7_CR@l
197        mtdcr   ebccfgd,r4
198
199/*      addis   r4,r0,FPGA_BRDC@h */
200/*      ori     r4,r4,FPGA_BRDC@l */
201/*      lbz     r3,0(r4)                /###*get FPGA board control reg */
202/*      eieio */
203/*      ori     r3,r3,0x01              /###*set UART1 control to select CTS/RTS */
204/*      stb     r3,0(r4) */
205
206        nop                             /* pass2 DCR errata #8 */
207        blr
208
209/*----------------------------------------------------------------------------- */
210/* Function:     sdram_init */
211/* Description:  Configures SDRAM memory banks on ERIC. */
212/*               We do manually init our SDRAM. */
213/*               If we have two SDRAM banks, simply undef SINGLE_BANK (ROLF :-) */
214/*               It is assumed that a 32MB 12x8(2) SDRAM is used. */
215/*----------------------------------------------------------------------------- */
216        .globl  sdram_init
217
218sdram_init:
219
220        mflr    r31
221
222#ifdef CFG_SDRAM_MANUALLY
223        /*------------------------------------------------------------------- */
224        /* Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2) */
225        /*------------------------------------------------------------------- */
226
227        addi    r4,0,mem_mb0cf
228        mtdcr   memcfga,r4
229        addis   r4,0,MB0CF@h
230        ori     r4,r4,MB0CF@l
231        mtdcr   memcfgd,r4
232
233        /*------------------------------------------------------------------- */
234        /* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) */
235        /*------------------------------------------------------------------- */
236
237        addi    r4,0,mem_mb1cf
238        mtdcr   memcfga,r4
239        addis   r4,0,MB1CF@h
240        ori     r4,r4,MB1CF@l
241        mtdcr   memcfgd,r4
242
243        /*------------------------------------------------------------------- */
244        /* Set MB2CF for bank 2. off */
245        /*------------------------------------------------------------------- */
246
247        addi    r4,0,mem_mb2cf
248        mtdcr   memcfga,r4
249        addis   r4,0,MB2CF@h
250        ori     r4,r4,MB2CF@l
251        mtdcr   memcfgd,r4
252
253        /*------------------------------------------------------------------- */
254        /* Set MB3CF for bank 3. off */
255        /*------------------------------------------------------------------- */
256
257        addi    r4,0,mem_mb3cf
258        mtdcr   memcfga,r4
259        addis   r4,0,MB3CF@h
260        ori     r4,r4,MB3CF@l
261        mtdcr   memcfgd,r4
262
263        /*------------------------------------------------------------------- */
264        /* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */
265        /* To set the appropriate timings, we need to know the SDRAM speed. */
266        /* We can use the PLB speed since the SDRAM speed is the same as */
267        /* the PLB speed. The PLB speed is the FBK divider times the */
268        /* 405GP reference clock, which on the Walnut board is 33Mhz. */
269        /* Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is */
270        /* 100Mhz; if FBK is 3, SDRAM is 133Mhz. */
271        /* NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and */
272        /* maybe 133Mhz. */
273        /*------------------------------------------------------------------- */
274
275        mfdcr   r5,strap                 /* determine FBK divider */
276                                          /* via STRAP reg to calc PLB speed. */
277                                          /* SDRAM speed is the same as the PLB */
278                                          /* speed. */
279        rlwinm  r4,r5,4,0x3             /* get FBK divide bits */
280
281..chk_66:
282        cmpi    %cr0,0,r4,0x1
283        bne     ..chk_100
284        addis   r6,0,SDTR_66@h          /* SDTR1 value for 66Mhz */
285        ori     r6,r6,SDTR_66@l
286        addis   r7,0,RTR_66             /* RTR value for 66Mhz */
287        b       ..sdram_ok
288..chk_100:
289        cmpi    %cr0,0,r4,0x2
290        bne     ..chk_133
291        addis   r6,0,SDTR_100@h        /* SDTR1 value for 100Mhz */
292        ori     r6,r6,SDTR_100@l
293        addis   r7,0,RTR_100           /* RTR value for 100Mhz */
294        b       ..sdram_ok
295..chk_133:
296        addis   r6,0,0x0107            /* SDTR1 value for 133Mhz */
297        ori     r6,r6,0x4015
298        addis   r7,0,0x07F0            /* RTR value for 133Mhz */
299
300..sdram_ok:
301        /*------------------------------------------------------------------- */
302        /* Set SDTR1 */
303        /*------------------------------------------------------------------- */
304        addi    r4,0,mem_sdtr1
305        mtdcr   memcfga,r4
306        mtdcr   memcfgd,r6
307
308        /*------------------------------------------------------------------- */
309        /* Set RTR */
310        /*------------------------------------------------------------------- */
311        addi    r4,0,mem_rtr
312        mtdcr   memcfga,r4
313        mtdcr   memcfgd,r7
314
315        /*------------------------------------------------------------------- */
316        /* Delay to ensure 200usec have elapsed since reset. Assume worst */
317        /* case that the core is running 200Mhz: */
318        /*   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
319        /*------------------------------------------------------------------- */
320        addis   r3,0,0x0000
321        ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
322        mtctr   r3
323..spinlp2:
324        bdnz    ..spinlp2               /* spin loop */
325
326        /*------------------------------------------------------------------- */
327        /* Set memory controller options reg, MCOPT1. */
328        /* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */
329        /* read/prefetch. */
330        /*------------------------------------------------------------------- */
331        addi    r4,0,mem_mcopt1
332        mtdcr   memcfga,r4
333        addis   r4,0,0x8080             /* set DC_EN=1 */
334        ori     r4,r4,0x0000
335        mtdcr   memcfgd,r4
336
337        /*------------------------------------------------------------------- */
338        /* Delay to ensure 10msec have elapsed since reset. This is */
339        /* required for the MPC952 to stabalize. Assume worst */
340        /* case that the core is running 200Mhz: */
341        /*   200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */
342        /* This delay should occur before accessing SDRAM. */
343        /*------------------------------------------------------------------- */
344        addis   r3,0,0x001E
345        ori     r3,r3,0x8480          /* ensure 10msec have passed since reset */
346        mtctr   r3
347..spinlp3:
348        bdnz    ..spinlp3                /* spin loop */
349
350#else
351/*fixme: do SDRAM Autoconfig from EEPROM here */
352
353#endif
354        mtlr    r31                     /* restore lr */
355        blr
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