source: SVN/rincon/u-boot/board/esd/common/s1d13806_1024_768_8bpp.h @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 23 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 6.7 KB
Line 
1/*
2 *
3 *  File generated by S1D13806CFG.EXE
4 *
5 *  Copyright (c) 2000,2001 Epson Research and Development, Inc.
6 *  All rights reserved.
7 *
8 *  PLEASE NOTE: If you FTP this file to a non-Windows platform, make
9 *               sure you transfer this file using ASCII, not BINARY mode.
10 *
11 * Panel:  (active)   1024x768 34Hz TFT Single 12-bit (PCLK=BUSCLK=33.333MHz)
12 * Memory: Embedded SDRAM (MCLK=CLKI=49.100MHz) (BUSCLK=33.333MHz)
13 *
14 */
15
16static S1D_REGS regs_13806_1024_768_8bpp[] =
17{
18        {0x0001,0x00},   /* Miscellaneous Register */
19        {0x01FC,0x00},   /* Display Mode Register */
20        {0x0004,0x00},   /* General IO Pins Configuration Register 0 */
21        {0x0005,0x00},   /* General IO Pins Configuration Register 1 */
22        {0x0008,0x00},   /* General IO Pins Control Register 0 */
23        {0x0009,0x00},   /* General IO Pins Control Register 1 */
24        {0x0010,0x00},   /* Memory Clock Configuration Register */
25        {0x0014,0x01},   /* LCD Pixel Clock Configuration Register */
26        {0x0018,0x00},   /* CRT/TV Pixel Clock Configuration Register */
27        {0x001C,0x02},   /* MediaPlug Clock Configuration Register */
28        {0x001E,0x01},   /* CPU To Memory Wait State Select Register */
29        {0x0021,0x03},   /* DRAM Refresh Rate Register */
30        {0x002A,0x00},   /* DRAM Timings Control Register 0 */
31        {0x002B,0x01},   /* DRAM Timings Control Register 1 */
32        {0x0020,0x80},   /* Memory Configuration Register */
33        {0x0030,0x55},   /* Panel Type Register */
34        {0x0031,0x00},   /* MOD Rate Register */
35        {0x0032,0x7F},   /* LCD Horizontal Display Width Register */
36        {0x0034,0x12},   /* LCD Horizontal Non-Display Period Register */
37        {0x0035,0x01},   /* TFT FPLINE Start Position Register */
38        {0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
39        {0x0038,0xFF},   /* LCD Vertical Display Height Register 0 */
40        {0x0039,0x02},   /* LCD Vertical Display Height Register 1 */
41        {0x003A,0x2C},   /* LCD Vertical Non-Display Period Register */
42        {0x003B,0x0A},   /* TFT FPFRAME Start Position Register */
43        {0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
44        {0x0040,0x03},   /* LCD Display Mode Register */
45        {0x0041,0x00},   /* LCD Miscellaneous Register */
46        {0x0042,0x00},   /* LCD Display Start Address Register 0 */
47        {0x0043,0x00},   /* LCD Display Start Address Register 1 */
48        {0x0044,0x00},   /* LCD Display Start Address Register 2 */
49        {0x0046,0x00},   /* LCD Memory Address Offset Register 0 */
50        {0x0047,0x02},   /* LCD Memory Address Offset Register 1 */
51        {0x0048,0x00},   /* LCD Pixel Panning Register */
52        {0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
53        {0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
54        {0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
55        {0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
56        {0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
57        {0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
58        {0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
59        {0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
60        {0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
61        {0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
62        {0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
63        {0x005B,0x10},   /* TV Output Control Register */
64        {0x0060,0x03},   /* CRT/TV Display Mode Register */
65        {0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
66        {0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
67        {0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
68        {0x0066,0x40},   /* CRT/TV Memory Address Offset Register 0 */
69        {0x0067,0x01},   /* CRT/TV Memory Address Offset Register 1 */
70        {0x0068,0x00},   /* CRT/TV Pixel Panning Register */
71        {0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
72        {0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
73        {0x0070,0x00},   /* LCD Ink/Cursor Control Register */
74        {0x0071,0x01},   /* LCD Ink/Cursor Start Address Register */
75        {0x0072,0x00},   /* LCD Cursor X Position Register 0 */
76        {0x0073,0x00},   /* LCD Cursor X Position Register 1 */
77        {0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
78        {0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
79        {0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
80        {0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
81        {0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
82        {0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
83        {0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
84        {0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
85        {0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
86        {0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
87        {0x0081,0x01},   /* CRT/TV Ink/Cursor Start Address Register */
88        {0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
89        {0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
90        {0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
91        {0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
92        {0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
93        {0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
94        {0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
95        {0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
96        {0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
97        {0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
98        {0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
99        {0x0100,0x00},   /* BitBlt Control Register 0 */
100        {0x0101,0x00},   /* BitBlt Control Register 1 */
101        {0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
102        {0x0103,0x00},   /* BitBlt Operation Register */
103        {0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
104        {0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
105        {0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
106        {0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
107        {0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
108        {0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
109        {0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
110        {0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
111        {0x0110,0x00},   /* BitBlt Width Register 0 */
112        {0x0111,0x00},   /* BitBlt Width Register 1 */
113        {0x0112,0x00},   /* BitBlt Height Register 0 */
114        {0x0113,0x00},   /* BitBlt Height Register 1 */
115        {0x0114,0x00},   /* BitBlt Background Color Register 0 */
116        {0x0115,0x00},   /* BitBlt Background Color Register 1 */
117        {0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
118        {0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
119        {0x01E0,0x00},   /* Look-Up Table Mode Register */
120        {0x01E2,0x00},   /* Look-Up Table Address Register */
121        {0x01F0,0x10},   /* Power Save Configuration Register */
122        {0x01F1,0x00},   /* Power Save Status Register */
123        {0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
124        {0x01FC,0x01},   /* Display Mode Register */
125};
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