source: SVN/rincon/u-boot/board/esd/du405/du405.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 2 years ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 4.7 KB
Line 
1/*
2 * (C) Copyright 2000, 2001
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include "du405.h"
26#include <asm/processor.h>
27#include <ppc4xx.h>
28#include <4xx_i2c.h>
29#include <command.h>
30
31DECLARE_GLOBAL_DATA_PTR;
32
33/*cmd_boot.c*/
34
35extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
36extern void lxt971_no_sleep(void);
37
38
39#if 0
40#define FPGA_DEBUG
41#endif
42
43#if 0
44#define FPGA_DEBUG2
45#endif
46
47/* fpga configuration data - generated by bin2cc */
48const unsigned char fpgadata[] = {
49#include "fpgadata.c"
50};
51
52/*
53 * include common fpga code (for esd boards)
54 */
55#include "../common/fpga.c"
56
57
58int board_early_init_f (void)
59{
60        int index, len, i;
61        int status;
62
63#ifdef FPGA_DEBUG
64        /* set up serial port with default baudrate */
65        (void) get_clocks ();
66        gd->baudrate = CONFIG_BAUDRATE;
67        serial_init ();
68        console_init_f ();
69#endif
70
71        /*
72         * Boot onboard FPGA
73         */
74        status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
75        if (status != 0) {
76                /* booting FPGA failed */
77#ifndef FPGA_DEBUG
78                /* set up serial port with default baudrate */
79                (void) get_clocks ();
80                gd->baudrate = CONFIG_BAUDRATE;
81                serial_init ();
82                console_init_f ();
83#endif
84                printf ("\nFPGA: Booting failed ");
85                switch (status) {
86                case ERROR_FPGA_PRG_INIT_LOW:
87                        printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
88                        break;
89                case ERROR_FPGA_PRG_INIT_HIGH:
90                        printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
91                        break;
92                case ERROR_FPGA_PRG_DONE:
93                        printf ("(Timeout: DONE not high after programming FPGA)\n ");
94                        break;
95                }
96
97                /* display infos on fpgaimage */
98                index = 15;
99                for (i = 0; i < 4; i++) {
100                        len = fpgadata[index];
101                        printf ("FPGA: %s\n", &(fpgadata[index + 1]));
102                        index += len + 3;
103                }
104                putc ('\n');
105                /* delayed reboot */
106                for (i = 20; i > 0; i--) {
107                        printf ("Rebooting in %2d seconds \r", i);
108                        for (index = 0; index < 1000; index++)
109                                udelay (1000);
110                }
111                putc ('\n');
112                do_reset (NULL, 0, 0, NULL);
113        }
114
115        /*
116         * IRQ 0-15  405GP internally generated; active high; level sensitive
117         * IRQ 16    405GP internally generated; active low; level sensitive
118         * IRQ 17-24 RESERVED
119         * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
120         * IRQ 26 (EXT IRQ 1) DUART_A; active high; level sensitive
121         * IRQ 27 (EXT IRQ 2) DUART_B; active high; level sensitive
122         * IRQ 28 (EXT IRQ 3) unused; active low; level sensitive
123         * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
124         * IRQ 30 (EXT IRQ 5) unused; active low; level sensitive
125         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
126         */
127        mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
128        mtdcr (uicer, 0x00000000);      /* disable all ints */
129        mtdcr (uiccr, 0x00000000);      /* set all to be non-critical */
130        mtdcr (uicpr, 0xFFFFFFB1);      /* set int polarities */
131        mtdcr (uictr, 0x10000000);      /* set int trigger levels */
132        mtdcr (uicvcr, 0x00000001);     /* set vect base=0,INT0 highest priority */
133        mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
134
135        /*
136         * EBC Configuration Register: set ready timeout to 100 us
137         */
138        mtebc (epcr, 0xb8400000);
139
140        return 0;
141}
142
143
144int misc_init_r (void)
145{
146        unsigned long cntrl0Reg;
147
148        /*
149         * Setup UART1 handshaking: use CTS instead of DSR
150         */
151        cntrl0Reg = mfdcr(cntrl0);
152        mtdcr(cntrl0, cntrl0Reg | 0x00001000);
153
154        return (0);
155}
156
157
158/*
159 * Check Board Identity:
160 */
161int checkboard (void)
162{
163        int index;
164        int len;
165        char str[64];
166        int i = getenv_r ("serial#", str, sizeof (str));
167
168        puts ("Board: ");
169
170        if (i == -1) {
171                puts ("### No HW ID - assuming DU405");
172        } else {
173                puts (str);
174        }
175
176        puts ("\nFPGA:  ");
177
178        /* display infos on fpgaimage */
179        index = 15;
180        for (i = 0; i < 4; i++) {
181                len = fpgadata[index];
182                printf ("%s ", &(fpgadata[index + 1]));
183                index += len + 3;
184        }
185
186        putc ('\n');
187
188        /*
189         * Reset external DUART via FPGA
190         */
191        *(volatile unsigned char *) FPGA_MODE_REG = 0xff;       /* reset high active */
192        *(volatile unsigned char *) FPGA_MODE_REG = 0x00;       /* low again */
193
194        /*
195         * Disable sleep mode in LXT971
196         */
197        lxt971_no_sleep();
198
199        return 0;
200}
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