1 | /* |
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2 | * (C) Copyright 2000, 2001 |
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3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
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4 | * |
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5 | * See file CREDITS for list of people who contributed to this |
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6 | * project. |
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7 | * |
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8 | * This program is free software; you can redistribute it and/or |
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9 | * modify it under the terms of the GNU General Public License as |
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10 | * published by the Free Software Foundation; either version 2 of |
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11 | * the License, or (at your option) any later version. |
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12 | * |
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13 | * This program is distributed in the hope that it will be useful, |
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14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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16 | * GNU General Public License for more details. |
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17 | * |
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18 | * You should have received a copy of the GNU General Public License |
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19 | * along with this program; if not, write to the Free Software |
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20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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21 | * MA 02111-1307 USA |
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22 | */ |
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23 | |
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24 | #include <common.h> |
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25 | #include "du405.h" |
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26 | #include <asm/processor.h> |
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27 | #include <ppc4xx.h> |
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28 | #include <4xx_i2c.h> |
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29 | #include <command.h> |
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30 | |
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31 | DECLARE_GLOBAL_DATA_PTR; |
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32 | |
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33 | /*cmd_boot.c*/ |
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34 | |
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35 | extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); |
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36 | extern void lxt971_no_sleep(void); |
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37 | |
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38 | |
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39 | #if 0 |
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40 | #define FPGA_DEBUG |
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41 | #endif |
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42 | |
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43 | #if 0 |
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44 | #define FPGA_DEBUG2 |
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45 | #endif |
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46 | |
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47 | /* fpga configuration data - generated by bin2cc */ |
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48 | const unsigned char fpgadata[] = { |
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49 | #include "fpgadata.c" |
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50 | }; |
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51 | |
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52 | /* |
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53 | * include common fpga code (for esd boards) |
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54 | */ |
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55 | #include "../common/fpga.c" |
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56 | |
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57 | |
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58 | int board_early_init_f (void) |
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59 | { |
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60 | int index, len, i; |
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61 | int status; |
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62 | |
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63 | #ifdef FPGA_DEBUG |
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64 | /* set up serial port with default baudrate */ |
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65 | (void) get_clocks (); |
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66 | gd->baudrate = CONFIG_BAUDRATE; |
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67 | serial_init (); |
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68 | console_init_f (); |
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69 | #endif |
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70 | |
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71 | /* |
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72 | * Boot onboard FPGA |
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73 | */ |
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74 | status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata)); |
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75 | if (status != 0) { |
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76 | /* booting FPGA failed */ |
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77 | #ifndef FPGA_DEBUG |
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78 | /* set up serial port with default baudrate */ |
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79 | (void) get_clocks (); |
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80 | gd->baudrate = CONFIG_BAUDRATE; |
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81 | serial_init (); |
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82 | console_init_f (); |
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83 | #endif |
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84 | printf ("\nFPGA: Booting failed "); |
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85 | switch (status) { |
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86 | case ERROR_FPGA_PRG_INIT_LOW: |
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87 | printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); |
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88 | break; |
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89 | case ERROR_FPGA_PRG_INIT_HIGH: |
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90 | printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); |
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91 | break; |
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92 | case ERROR_FPGA_PRG_DONE: |
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93 | printf ("(Timeout: DONE not high after programming FPGA)\n "); |
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94 | break; |
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95 | } |
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96 | |
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97 | /* display infos on fpgaimage */ |
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98 | index = 15; |
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99 | for (i = 0; i < 4; i++) { |
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100 | len = fpgadata[index]; |
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101 | printf ("FPGA: %s\n", &(fpgadata[index + 1])); |
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102 | index += len + 3; |
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103 | } |
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104 | putc ('\n'); |
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105 | /* delayed reboot */ |
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106 | for (i = 20; i > 0; i--) { |
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107 | printf ("Rebooting in %2d seconds \r", i); |
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108 | for (index = 0; index < 1000; index++) |
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109 | udelay (1000); |
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110 | } |
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111 | putc ('\n'); |
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112 | do_reset (NULL, 0, 0, NULL); |
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113 | } |
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114 | |
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115 | /* |
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116 | * IRQ 0-15 405GP internally generated; active high; level sensitive |
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117 | * IRQ 16 405GP internally generated; active low; level sensitive |
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118 | * IRQ 17-24 RESERVED |
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119 | * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive |
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120 | * IRQ 26 (EXT IRQ 1) DUART_A; active high; level sensitive |
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121 | * IRQ 27 (EXT IRQ 2) DUART_B; active high; level sensitive |
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122 | * IRQ 28 (EXT IRQ 3) unused; active low; level sensitive |
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123 | * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive |
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124 | * IRQ 30 (EXT IRQ 5) unused; active low; level sensitive |
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125 | * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive |
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126 | */ |
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127 | mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ |
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128 | mtdcr (uicer, 0x00000000); /* disable all ints */ |
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129 | mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ |
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130 | mtdcr (uicpr, 0xFFFFFFB1); /* set int polarities */ |
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131 | mtdcr (uictr, 0x10000000); /* set int trigger levels */ |
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132 | mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ |
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133 | mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ |
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134 | |
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135 | /* |
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136 | * EBC Configuration Register: set ready timeout to 100 us |
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137 | */ |
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138 | mtebc (epcr, 0xb8400000); |
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139 | |
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140 | return 0; |
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141 | } |
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142 | |
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143 | |
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144 | int misc_init_r (void) |
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145 | { |
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146 | unsigned long cntrl0Reg; |
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147 | |
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148 | /* |
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149 | * Setup UART1 handshaking: use CTS instead of DSR |
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150 | */ |
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151 | cntrl0Reg = mfdcr(cntrl0); |
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152 | mtdcr(cntrl0, cntrl0Reg | 0x00001000); |
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153 | |
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154 | return (0); |
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155 | } |
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156 | |
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157 | |
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158 | /* |
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159 | * Check Board Identity: |
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160 | */ |
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161 | int checkboard (void) |
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162 | { |
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163 | int index; |
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164 | int len; |
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165 | char str[64]; |
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166 | int i = getenv_r ("serial#", str, sizeof (str)); |
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167 | |
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168 | puts ("Board: "); |
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169 | |
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170 | if (i == -1) { |
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171 | puts ("### No HW ID - assuming DU405"); |
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172 | } else { |
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173 | puts (str); |
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174 | } |
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175 | |
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176 | puts ("\nFPGA: "); |
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177 | |
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178 | /* display infos on fpgaimage */ |
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179 | index = 15; |
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180 | for (i = 0; i < 4; i++) { |
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181 | len = fpgadata[index]; |
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182 | printf ("%s ", &(fpgadata[index + 1])); |
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183 | index += len + 3; |
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184 | } |
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185 | |
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186 | putc ('\n'); |
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187 | |
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188 | /* |
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189 | * Reset external DUART via FPGA |
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190 | */ |
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191 | *(volatile unsigned char *) FPGA_MODE_REG = 0xff; /* reset high active */ |
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192 | *(volatile unsigned char *) FPGA_MODE_REG = 0x00; /* low again */ |
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193 | |
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194 | /* |
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195 | * Disable sleep mode in LXT971 |
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196 | */ |
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197 | lxt971_no_sleep(); |
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198 | |
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199 | return 0; |
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200 | } |
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