source: SVN/rincon/u-boot/board/esd/pci405/writeibm.S @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 4.9 KB
Line 
1/*------------------------------------------------------------------------------+ */
2/* */
3/*       This source code has been made available to you by IBM on an AS-IS */
4/*       basis.  Anyone receiving this source is licensed under IBM */
5/*       copyrights to use it in any way he or she deems fit, including */
6/*       copying it, modifying it, compiling it, and redistributing it either */
7/*       with or without modifications.  No license under IBM patents or */
8/*       patent applications is to be implied by the copyright license. */
9/* */
10/*       Any user of this software should understand that IBM cannot provide */
11/*       technical support for this software and will not be responsible for */
12/*       any consequences resulting from the use of this software. */
13/* */
14/*       Any person who transfers this source code or any derivative work */
15/*       must include the IBM copyright notice, this paragraph, and the */
16/*       preceding two paragraphs in the transferred software. */
17/* */
18/*       COPYRIGHT   I B M   CORPORATION 1995 */
19/*       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M */
20/*------------------------------------------------------------------------------- */
21
22/*----------------------------------------------------------------------------- */
23/* Function:     ext_bus_cntlr_init */
24/* Description:  Initializes the External Bus Controller for the external */
25/*              peripherals. IMPORTANT: For pass1 this code must run from */
26/*              cache since you can not reliably change a peripheral banks */
27/*              timing register (pbxap) while running code from that bank. */
28/*              For ex., since we are running from ROM on bank 0, we can NOT */
29/*              execute the code that modifies bank 0 timings from ROM, so */
30/*              we run it from cache. */
31/*      Bank 0 - Flash and SRAM */
32/*      Bank 1 - NVRAM/RTC */
33/*      Bank 2 - Keyboard/Mouse controller */
34/*      Bank 3 - IR controller */
35/*      Bank 4 - not used */
36/*      Bank 5 - not used */
37/*      Bank 6 - not used */
38/*      Bank 7 - FPGA registers */
39/*----------------------------------------------------------------------------- */
40#include <ppc4xx.h>
41
42#include <ppc_asm.tmpl>
43#include <ppc_defs.h>
44
45#include <asm/cache.h>
46#include <asm/mmu.h>
47
48
49        .globl  write_without_sync
50write_without_sync:
51                /*
52                 * Write one values to host via pci busmastering
53                 * ptr = 0xc0000000 -> 0x01000000 (PCI)
54                 * *ptr = 0x01234567;
55                 */
56        addi    r31,0,0
57        lis     r31,0xc000
58
59start1:
60        lis     r0,0x0123
61        ori     r0,r0,0x4567
62        stw     r0,0(r31)
63
64                /*
65                 * Read one value back
66                 * ptr = (volatile unsigned long *)addr;
67                 * val = *ptr;
68                 */
69
70        lwz     r0,0(r31)
71
72                /*
73                 * One pci config write
74                 * ibmPciConfigWrite(0x2e, 2, 0x1234);
75                 */
76                /* subsystem id */
77
78        li      r4,0x002C
79        oris    r4,r4,0x8000
80        lis     r3,0xEEC0
81        stwbrx  r4,0,r3
82
83        li      r5,0x1234
84        ori     r3,r3,0x4
85        stwbrx  r5,0,r3
86
87        b       start1
88
89        blr     /* never reached !!!! */
90
91        .globl  write_with_sync
92write_with_sync:
93                /*
94                 * Write one values to host via pci busmastering
95                 * ptr = 0xc0000000 -> 0x01000000 (PCI)
96                 * *ptr = 0x01234567;
97                 */
98        addi    r31,0,0
99        lis     r31,0xc000
100
101start2:
102        lis     r0,0x0123
103        ori     r0,r0,0x4567
104        stw     r0,0(r31)
105
106                /*
107                 * Read one value back
108                 * ptr = (volatile unsigned long *)addr;
109                 * val = *ptr;
110                 */
111
112        lwz     r0,0(r31)
113
114                /*
115                 * One pci config write
116                 * ibmPciConfigWrite(0x2e, 2, 0x1234);
117                 */
118                /* subsystem id */
119
120        li      r4,0x002C
121        oris    r4,r4,0x8000
122        lis     r3,0xEEC0
123        stwbrx  r4,0,r3
124        sync
125
126        li      r5,0x1234
127        ori     r3,r3,0x4
128        stwbrx  r5,0,r3
129        sync
130
131        b       start2
132
133        blr     /* never reached !!!! */
134
135        .globl  write_with_less_sync
136write_with_less_sync:
137                /*
138                 * Write one values to host via pci busmastering
139                 * ptr = 0xc0000000 -> 0x01000000 (PCI)
140                 * *ptr = 0x01234567;
141                 */
142        addi    r31,0,0
143        lis     r31,0xc000
144
145start2b:
146        lis     r0,0x0123
147        ori     r0,r0,0x4567
148        stw     r0,0(r31)
149
150                /*
151                 * Read one value back
152                 * ptr = (volatile unsigned long *)addr;
153                 * val = *ptr;
154                 */
155
156        lwz     r0,0(r31)
157
158                /*
159                 * One pci config write
160                 * ibmPciConfigWrite(0x2e, 2, 0x1234);
161                 */
162                /* subsystem id */
163
164        li      r4,0x002C
165        oris    r4,r4,0x8000
166        lis     r3,0xEEC0
167        stwbrx  r4,0,r3
168        sync
169
170        li      r5,0x1234
171        ori     r3,r3,0x4
172        stwbrx  r5,0,r3
173/*        sync */
174
175        b       start2b
176
177        blr     /* never reached !!!! */
178
179        .globl  write_with_more_sync
180write_with_more_sync:
181                /*
182                 * Write one values to host via pci busmastering
183                 * ptr = 0xc0000000 -> 0x01000000 (PCI)
184                 * *ptr = 0x01234567;
185                 */
186        addi    r31,0,0
187        lis     r31,0xc000
188
189start3:
190        lis     r0,0x0123
191        ori     r0,r0,0x4567
192        stw     r0,0(r31)
193        sync
194
195                /*
196                 * Read one value back
197                 * ptr = (volatile unsigned long *)addr;
198                 * val = *ptr;
199                 */
200
201        lwz     r0,0(r31)
202        sync
203
204                /*
205                 * One pci config write
206                 * ibmPciConfigWrite(0x2e, 2, 0x1234);
207                 */
208                /* subsystem id (PCIC0_SBSYSVID)*/
209
210        li      r4,0x002C
211        oris    r4,r4,0x8000
212        lis     r3,0xEEC0
213        stwbrx  r4,0,r3
214        sync
215
216        li      r5,0x1234
217        ori     r3,r3,0x4
218        stwbrx  r5,0,r3
219        sync
220
221        b       start3
222
223        blr     /* never reached !!!! */
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