1 | /*------------------------------------------------------------------------------+ */ |
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2 | /* */ |
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3 | /* This source code has been made available to you by IBM on an AS-IS */ |
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4 | /* basis. Anyone receiving this source is licensed under IBM */ |
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5 | /* copyrights to use it in any way he or she deems fit, including */ |
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6 | /* copying it, modifying it, compiling it, and redistributing it either */ |
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7 | /* with or without modifications. No license under IBM patents or */ |
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8 | /* patent applications is to be implied by the copyright license. */ |
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9 | /* */ |
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10 | /* Any user of this software should understand that IBM cannot provide */ |
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11 | /* technical support for this software and will not be responsible for */ |
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12 | /* any consequences resulting from the use of this software. */ |
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13 | /* */ |
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14 | /* Any person who transfers this source code or any derivative work */ |
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15 | /* must include the IBM copyright notice, this paragraph, and the */ |
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16 | /* preceding two paragraphs in the transferred software. */ |
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17 | /* */ |
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18 | /* COPYRIGHT I B M CORPORATION 1995 */ |
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19 | /* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ |
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20 | /*------------------------------------------------------------------------------- */ |
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21 | |
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22 | /*----------------------------------------------------------------------------- */ |
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23 | /* Function: ext_bus_cntlr_init */ |
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24 | /* Description: Initializes the External Bus Controller for the external */ |
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25 | /* peripherals. IMPORTANT: For pass1 this code must run from */ |
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26 | /* cache since you can not reliably change a peripheral banks */ |
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27 | /* timing register (pbxap) while running code from that bank. */ |
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28 | /* For ex., since we are running from ROM on bank 0, we can NOT */ |
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29 | /* execute the code that modifies bank 0 timings from ROM, so */ |
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30 | /* we run it from cache. */ |
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31 | /* Bank 0 - Flash and SRAM */ |
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32 | /* Bank 1 - NVRAM/RTC */ |
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33 | /* Bank 2 - Keyboard/Mouse controller */ |
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34 | /* Bank 3 - IR controller */ |
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35 | /* Bank 4 - not used */ |
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36 | /* Bank 5 - not used */ |
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37 | /* Bank 6 - not used */ |
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38 | /* Bank 7 - FPGA registers */ |
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39 | /*----------------------------------------------------------------------------- */ |
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40 | #include <ppc4xx.h> |
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41 | |
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42 | #include <ppc_asm.tmpl> |
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43 | #include <ppc_defs.h> |
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44 | |
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45 | #include <asm/cache.h> |
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46 | #include <asm/mmu.h> |
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47 | |
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48 | |
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49 | .globl write_without_sync |
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50 | write_without_sync: |
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51 | /* |
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52 | * Write one values to host via pci busmastering |
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53 | * ptr = 0xc0000000 -> 0x01000000 (PCI) |
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54 | * *ptr = 0x01234567; |
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55 | */ |
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56 | addi r31,0,0 |
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57 | lis r31,0xc000 |
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58 | |
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59 | start1: |
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60 | lis r0,0x0123 |
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61 | ori r0,r0,0x4567 |
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62 | stw r0,0(r31) |
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63 | |
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64 | /* |
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65 | * Read one value back |
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66 | * ptr = (volatile unsigned long *)addr; |
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67 | * val = *ptr; |
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68 | */ |
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69 | |
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70 | lwz r0,0(r31) |
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71 | |
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72 | /* |
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73 | * One pci config write |
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74 | * ibmPciConfigWrite(0x2e, 2, 0x1234); |
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75 | */ |
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76 | /* subsystem id */ |
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77 | |
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78 | li r4,0x002C |
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79 | oris r4,r4,0x8000 |
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80 | lis r3,0xEEC0 |
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81 | stwbrx r4,0,r3 |
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82 | |
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83 | li r5,0x1234 |
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84 | ori r3,r3,0x4 |
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85 | stwbrx r5,0,r3 |
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86 | |
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87 | b start1 |
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88 | |
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89 | blr /* never reached !!!! */ |
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90 | |
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91 | .globl write_with_sync |
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92 | write_with_sync: |
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93 | /* |
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94 | * Write one values to host via pci busmastering |
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95 | * ptr = 0xc0000000 -> 0x01000000 (PCI) |
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96 | * *ptr = 0x01234567; |
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97 | */ |
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98 | addi r31,0,0 |
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99 | lis r31,0xc000 |
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100 | |
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101 | start2: |
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102 | lis r0,0x0123 |
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103 | ori r0,r0,0x4567 |
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104 | stw r0,0(r31) |
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105 | |
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106 | /* |
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107 | * Read one value back |
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108 | * ptr = (volatile unsigned long *)addr; |
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109 | * val = *ptr; |
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110 | */ |
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111 | |
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112 | lwz r0,0(r31) |
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113 | |
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114 | /* |
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115 | * One pci config write |
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116 | * ibmPciConfigWrite(0x2e, 2, 0x1234); |
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117 | */ |
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118 | /* subsystem id */ |
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119 | |
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120 | li r4,0x002C |
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121 | oris r4,r4,0x8000 |
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122 | lis r3,0xEEC0 |
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123 | stwbrx r4,0,r3 |
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124 | sync |
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125 | |
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126 | li r5,0x1234 |
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127 | ori r3,r3,0x4 |
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128 | stwbrx r5,0,r3 |
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129 | sync |
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130 | |
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131 | b start2 |
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132 | |
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133 | blr /* never reached !!!! */ |
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134 | |
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135 | .globl write_with_less_sync |
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136 | write_with_less_sync: |
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137 | /* |
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138 | * Write one values to host via pci busmastering |
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139 | * ptr = 0xc0000000 -> 0x01000000 (PCI) |
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140 | * *ptr = 0x01234567; |
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141 | */ |
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142 | addi r31,0,0 |
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143 | lis r31,0xc000 |
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144 | |
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145 | start2b: |
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146 | lis r0,0x0123 |
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147 | ori r0,r0,0x4567 |
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148 | stw r0,0(r31) |
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149 | |
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150 | /* |
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151 | * Read one value back |
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152 | * ptr = (volatile unsigned long *)addr; |
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153 | * val = *ptr; |
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154 | */ |
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155 | |
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156 | lwz r0,0(r31) |
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157 | |
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158 | /* |
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159 | * One pci config write |
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160 | * ibmPciConfigWrite(0x2e, 2, 0x1234); |
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161 | */ |
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162 | /* subsystem id */ |
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163 | |
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164 | li r4,0x002C |
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165 | oris r4,r4,0x8000 |
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166 | lis r3,0xEEC0 |
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167 | stwbrx r4,0,r3 |
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168 | sync |
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169 | |
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170 | li r5,0x1234 |
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171 | ori r3,r3,0x4 |
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172 | stwbrx r5,0,r3 |
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173 | /* sync */ |
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174 | |
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175 | b start2b |
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176 | |
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177 | blr /* never reached !!!! */ |
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178 | |
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179 | .globl write_with_more_sync |
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180 | write_with_more_sync: |
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181 | /* |
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182 | * Write one values to host via pci busmastering |
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183 | * ptr = 0xc0000000 -> 0x01000000 (PCI) |
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184 | * *ptr = 0x01234567; |
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185 | */ |
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186 | addi r31,0,0 |
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187 | lis r31,0xc000 |
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188 | |
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189 | start3: |
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190 | lis r0,0x0123 |
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191 | ori r0,r0,0x4567 |
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192 | stw r0,0(r31) |
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193 | sync |
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194 | |
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195 | /* |
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196 | * Read one value back |
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197 | * ptr = (volatile unsigned long *)addr; |
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198 | * val = *ptr; |
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199 | */ |
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200 | |
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201 | lwz r0,0(r31) |
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202 | sync |
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203 | |
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204 | /* |
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205 | * One pci config write |
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206 | * ibmPciConfigWrite(0x2e, 2, 0x1234); |
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207 | */ |
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208 | /* subsystem id (PCIC0_SBSYSVID)*/ |
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209 | |
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210 | li r4,0x002C |
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211 | oris r4,r4,0x8000 |
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212 | lis r3,0xEEC0 |
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213 | stwbrx r4,0,r3 |
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214 | sync |
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215 | |
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216 | li r5,0x1234 |
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217 | ori r3,r3,0x4 |
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218 | stwbrx r5,0,r3 |
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219 | sync |
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220 | |
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221 | b start3 |
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222 | |
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223 | blr /* never reached !!!! */ |
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