source: SVN/rincon/u-boot/board/esd/pmc405/pmc405.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 4.8 KB
Line 
1/*
2 * (C) Copyright 2001-2003
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2005
6 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <asm/processor.h>
29#include <command.h>
30#include <malloc.h>
31
32DECLARE_GLOBAL_DATA_PTR;
33
34extern void lxt971_no_sleep(void);
35
36/* fpga configuration data - not compressed, generated by bin2c */
37const unsigned char fpgadata[] =
38{
39#include "fpgadata.c"
40};
41int filesize = sizeof(fpgadata);
42
43
44int board_early_init_f (void)
45{
46        /*
47         * IRQ 0-15  405GP internally generated; active high; level sensitive
48         * IRQ 16    405GP internally generated; active low; level sensitive
49         * IRQ 17-24 RESERVED
50         * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
51         * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
52         * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
53         * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
54         * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
55         * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
56         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
57         */
58        mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
59        mtdcr(uicer, 0x00000000);       /* disable all ints */
60        mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
61        mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
62        mtdcr(uictr, 0x10000000);       /* set int trigger levels */
63        mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
64        mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
65
66        /*
67         * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
68         */
69        mtebc (epcr, 0xa8400000);
70
71        /*
72         * Setup GPIO pins
73         */
74
75        mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_FPGA_INIT | \
76                                        CFG_FPGA_DONE | \
77                                        CFG_XEREADY | \
78                                        CFG_NONMONARCH | \
79                                        CFG_REV1_2) << 5));
80
81        if (!(in32(GPIO0_IR) & CFG_REV1_2)) {
82                /* rev 1.2 boards */
83                mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_INTA_FAKE | \
84                                                CFG_SELF_RST) << 5));
85        }
86
87        out32(GPIO0_OR, 0);
88        out32(GPIO0_TCR, CFG_FPGA_PRG | CFG_FPGA_CLK | CFG_FPGA_DATA | CFG_XEREADY); /* setup for output */
89
90        /* - check if rev1_2 is low, then:
91         * - set/reset CFG_INTA_FAKE/CFG_SELF_RST in TCR to assert INTA# or SELFRST#
92         */
93
94        return 0;
95}
96
97
98/* ------------------------------------------------------------------------- */
99
100
101int misc_init_r (void)
102{
103        /* adjust flash start and offset */
104        gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
105        gd->bd->bi_flashoffset = 0;
106
107        out32(GPIO0_OR, in32(GPIO0_OR) | CFG_XEREADY); /* deassert EREADY# */
108        return (0);
109}
110
111ushort pmc405_pci_subsys_deviceid(void)
112{
113        ulong val;
114        val = in32(GPIO0_IR);
115        if (!(val & CFG_REV1_2)) { /* low=rev1.2 */
116                if (val & CFG_NONMONARCH) { /* monarch# signal */
117                        return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH;
118                }
119                return CFG_PCI_SUBSYS_DEVICEID_MONARCH;
120        }
121        return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH;
122}
123
124/*
125 * Check Board Identity:
126 */
127int checkboard (void)
128{
129        ulong val;
130
131        char str[64];
132        int i = getenv_r ("serial#", str, sizeof(str));
133
134        puts ("Board: ");
135
136        if (i == -1) {
137                puts ("### No HW ID - assuming PMC405");
138        } else {
139                puts(str);
140        }
141
142        val = in32(GPIO0_IR);
143        if (!(val & CFG_REV1_2)) { /* low=rev1.2 */
144                puts(" rev1.2 (");
145                if (val & CFG_NONMONARCH) { /* monarch# signal */
146                        puts("non-");
147                }
148                puts("monarch)");
149        } else {
150                puts(" <=rev1.1");
151        }
152
153        putc ('\n');
154
155        return 0;
156}
157
158/* ------------------------------------------------------------------------- */
159void reset_phy(void)
160{
161#ifdef CONFIG_LXT971_NO_SLEEP
162
163        /*
164         * Disable sleep mode in LXT971
165         */
166        lxt971_no_sleep();
167#endif
168}
169
170
171int do_cantest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
172{
173        ulong addr;
174        volatile uchar *ptr;
175        volatile uchar val;
176        int i;
177
178        addr = simple_strtol (argv[1], NULL, 16) + 0x16;
179
180        i = 0;
181        for (;;) {
182                ptr = (uchar *)addr;
183                for (i=0; i<8; i++) {
184                        *ptr = i;
185                        val = *ptr;
186
187                        if (val != i) {
188                                printf("ERROR: addr=%p write=0x%02X, read=0x%02X\n", ptr, i, val);
189                                return 0;
190                        }
191
192                        /* Abort if ctrl-c was pressed */
193                        if (ctrlc()) {
194                                puts("\nAbort\n");
195                                return 0;
196                        }
197
198                        ptr++;
199                }
200        }
201
202        return 0;
203}
204U_BOOT_CMD(
205        cantest,        3,      1,      do_cantest,
206        "cantest - Test CAN controller",
207        NULL
208        );
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