source: SVN/rincon/u-boot/board/esd/vom405/vom405.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 3.5 KB
Line 
1/*
2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/processor.h>
26#include <command.h>
27#include <malloc.h>
28
29DECLARE_GLOBAL_DATA_PTR;
30
31extern void lxt971_no_sleep(void);
32
33/* fpga configuration data - not compressed, generated by bin2c */
34const unsigned char fpgadata[] =
35{
36#include "fpgadata.c"
37};
38int filesize = sizeof(fpgadata);
39
40int board_early_init_f (void)
41{
42        /*
43         * IRQ 0-15  405GP internally generated; active high; level sensitive
44         * IRQ 16    405GP internally generated; active low; level sensitive
45         * IRQ 17-24 RESERVED
46         * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
47         * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
48         * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
49         * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
50         * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
51         * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
52         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
53         */
54        mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
55        mtdcr(uicer, 0x00000000);       /* disable all ints */
56        mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
57        mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
58        mtdcr(uictr, 0x10000000);       /* set int trigger levels */
59        mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
60        mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
61
62        /*
63         * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
64         */
65        mtebc (epcr, 0xa8400000); /* ebc always driven */
66
67        /*
68         * Reset CPLD via GPIO12 (CS3) pin
69         */
70        out32(GPIO0_OR, in32(GPIO0_OR) & ~(0x80000000 >> 12));
71        udelay(1000); /* wait 1ms */
72        out32(GPIO0_OR, in32(GPIO0_OR) | (0x80000000 >> 12));
73        udelay(1000); /* wait 1ms */
74
75        return 0;
76}
77
78int misc_init_r (void)
79{
80        /* adjust flash start and offset */
81        gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
82        gd->bd->bi_flashoffset = 0;
83
84        return (0);
85}
86
87/*
88 * Check Board Identity:
89 */
90int checkboard (void)
91{
92        char str[64];
93        int i = getenv_r ("serial#", str, sizeof(str));
94        int flashcnt;
95        int delay;
96        volatile unsigned char *led_reg = (unsigned char *)((ulong)CAN_BA + 0x1000);
97
98        puts ("Board: ");
99
100        if (i == -1) {
101                puts ("### No HW ID - assuming VOM405");
102        } else {
103                puts(str);
104        }
105
106        printf(" (PLD-Version=%02d)\n", *led_reg);
107
108        /*
109         * Flash LEDs
110         */
111        for (flashcnt = 0; flashcnt < 3; flashcnt++) {
112                *led_reg = 0x40;        /* LED_B..D off */
113                for (delay = 0; delay < 100; delay++)
114                        udelay(1000);
115                *led_reg = 0x47;        /* LED_B..D on */
116                for (delay = 0; delay < 50; delay++)
117                        udelay(1000);
118        }
119        *led_reg = 0x40;
120
121        return 0;
122}
123
124void reset_phy(void)
125{
126#ifdef CONFIG_LXT971_NO_SLEEP
127
128        /*
129         * Disable sleep mode in LXT971
130         */
131        lxt971_no_sleep();
132#endif
133}
Note: See TracBrowser for help on using the repository browser.