source: SVN/rincon/u-boot/board/etin/debris/speed.h @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 1.8 KB
Line 
1/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*-----------------------------------------------------------------------
25 * Timer value for timer 2, ICLK = 10
26 *
27 * SPEED_FCOUNT2 =  GCLK / (16 * (TIMER_TMR_PS + 1))
28 * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
29 *
30 * SPEED_FCOUNT2        timer 2 counting frequency
31 * GCLK                 CPU clock
32 * SPEED_TMR2_PS        prescaler
33 */
34#define SPEED_TMR2_PS   (250 - 1)       /* divide by 250        */
35
36/*-----------------------------------------------------------------------
37 * Timer value for PIT
38 *
39 * PIT_TIME = SPEED_PITC / PITRTCLK
40 * PITRTCLK = 8192
41 */
42#define SPEED_PITC      (82 << 16)      /* start counting from 82       */
43
44/*
45 * The new value for PTA is calculated from
46 *
47 *      PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
48 *
49 * gclk         CPU clock (not bus clock !)
50 * Trefresh     Refresh cycle * 4 (four word bursts used)
51 * DFBRG        For normal mode (no clock reduction) always 0
52 * PTP          Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
53 * NCS          Number of SDRAM banks (chip selects) on this UPM.
54 */
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