source: SVN/rincon/u-boot/board/evb64260/evb64260.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 11.1 KB
Line 
1/*
2 * (C) Copyright 2001
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * evb64260.c - main board support/init for the Galileo Eval board.
26 */
27
28#include <common.h>
29#include <74xx_7xx.h>
30#include <galileo/memory.h>
31#include <galileo/pci.h>
32#include <galileo/gt64260R.h>
33#include <net.h>
34#include <netdev.h>
35
36#include <asm/io.h>
37#include "eth.h"
38#include "mpsc.h"
39#include "i2c.h"
40#include "64260.h"
41
42DECLARE_GLOBAL_DATA_PTR;
43
44#ifdef CONFIG_ZUMA_V2
45extern void zuma_mbox_init(void);
46#endif
47
48#undef  DEBUG
49#define MAP_PCI
50
51#ifdef DEBUG
52#define DP(x) x
53#else
54#define DP(x)
55#endif
56
57/* ------------------------------------------------------------------------- */
58
59/* this is the current GT register space location */
60/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
61
62/* Unfortunately, we cant change it while we are in flash, so we initialize it
63 * to the "final" value. This means that any debug_led calls before
64 * board_early_init_f wont work right (like in cpu_init_f).
65 * See also my_remap_gt_regs below. (NTL)
66 */
67
68unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
69
70/* ------------------------------------------------------------------------- */
71
72/*
73 * This is a version of the GT register space remapping function that
74 * doesn't touch globals (meaning, it's ok to run from flash.)
75 *
76 * Unfortunately, this has the side effect that a writable
77 * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
78 */
79
80void
81my_remap_gt_regs(u32 cur_loc, u32 new_loc)
82{
83        u32 temp;
84
85        /* check and see if it's already moved */
86        temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
87        if ((temp & 0xffff) == new_loc >> 20)
88                return;
89
90        temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
91                0xffff0000) | (new_loc >> 20);
92
93        out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
94
95        while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
96}
97
98static void
99gt_pci_config(void)
100{
101        /* move PCI stuff out of the way - NTL */
102        /* map PCI Host 0 */
103        pciMapSpace(PCI_HOST0, PCI_REGION0, CFG_PCI0_0_MEM_SPACE,
104                CFG_PCI0_0_MEM_SPACE, CFG_PCI0_MEM_SIZE);
105
106        pciMapSpace(PCI_HOST0, PCI_REGION1, 0, 0, 0);
107        pciMapSpace(PCI_HOST0, PCI_REGION2, 0, 0, 0);
108        pciMapSpace(PCI_HOST0, PCI_REGION3, 0, 0, 0);
109
110        pciMapSpace(PCI_HOST0, PCI_IO, CFG_PCI0_IO_SPACE_PCI,
111                CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE);
112
113        /* map PCI Host 1 */
114        pciMapSpace(PCI_HOST1, PCI_REGION0, CFG_PCI1_0_MEM_SPACE,
115                CFG_PCI1_0_MEM_SPACE, CFG_PCI1_MEM_SIZE);
116
117        pciMapSpace(PCI_HOST1, PCI_REGION1, 0, 0, 0);
118        pciMapSpace(PCI_HOST1, PCI_REGION2, 0, 0, 0);
119        pciMapSpace(PCI_HOST1, PCI_REGION3, 0, 0, 0);
120
121        pciMapSpace(PCI_HOST1, PCI_IO, CFG_PCI1_IO_SPACE_PCI,
122                CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE);
123
124        /* PCI interface settings */
125        GT_REG_WRITE(PCI_0TIMEOUT_RETRY, 0xffff);
126        GT_REG_WRITE(PCI_1TIMEOUT_RETRY, 0xffff);
127        GT_REG_WRITE(PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e);
128        GT_REG_WRITE(PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e);
129
130
131}
132
133/* Setup CPU interface paramaters */
134static void
135gt_cpu_config(void)
136{
137        cpu_t cpu = get_cpu_type();
138        ulong tmp;
139
140        /* cpu configuration register */
141        tmp = GTREGREAD(CPU_CONFIGURATION);
142
143        /* set the AACK delay bit
144         * see Res#14 */
145        tmp |= CPU_CONF_AACK_DELAY;
146        tmp &= ~CPU_CONF_AACK_DELAY_2; /* New RGF */
147
148        /* Galileo claims this is necessary for all busses >= 100 MHz */
149        tmp |= CPU_CONF_FAST_CLK;
150
151        if (cpu == CPU_750CX) {
152                tmp &= ~CPU_CONF_DP_VALID; /* Safer, needed for CXe. RGF */
153                tmp &= ~CPU_CONF_AP_VALID;
154        } else {
155                tmp |= CPU_CONF_DP_VALID;
156                tmp |= CPU_CONF_AP_VALID;
157        }
158
159        /* this only works with the MPX bus */
160        tmp &= ~CPU_CONF_RD_OOO; /* Safer RGF */
161        tmp |= CPU_CONF_PIPELINE;
162        tmp |= CPU_CONF_TA_DELAY;
163
164        GT_REG_WRITE(CPU_CONFIGURATION, tmp);
165
166        /* CPU master control register */
167        tmp = GTREGREAD(CPU_MASTER_CONTROL);
168
169        tmp |= CPU_MAST_CTL_ARB_EN;
170
171        if ((cpu == CPU_7400) ||
172            (cpu == CPU_7410) ||
173            (cpu == CPU_7450)) {
174
175                tmp |= CPU_MAST_CTL_CLEAN_BLK;
176                tmp |= CPU_MAST_CTL_FLUSH_BLK;
177
178        } else {
179                /* cleanblock must be cleared for CPUs
180                 * that do not support this command
181                 * see Res#1 */
182                tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
183                tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
184        }
185        GT_REG_WRITE(CPU_MASTER_CONTROL, tmp);
186}
187
188/*
189 * board_early_init_f.
190 *
191 * set up gal. device mappings, etc.
192 */
193int board_early_init_f (void)
194{
195        uchar sram_boot = 0;
196
197        /*
198         * set up the GT the way the kernel wants it
199         * the call to move the GT register space will obviously
200         * fail if it has already been done, but we're going to assume
201         * that if it's not at the power-on location, it's where we put
202         * it last time. (huber)
203         */
204        my_remap_gt_regs(CFG_DFL_GT_REGS, CFG_GT_REGS);
205
206        gt_pci_config();
207
208        /* mask all external interrupt sources */
209        GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
210        GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
211        GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
212        GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
213        GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
214        GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
215        GT_REG_WRITE(CPU_INT_0_MASK, 0);
216        GT_REG_WRITE(CPU_INT_1_MASK, 0);
217        GT_REG_WRITE(CPU_INT_2_MASK, 0);
218        GT_REG_WRITE(CPU_INT_3_MASK, 0);
219
220        /* now, onto the configuration */
221        GT_REG_WRITE(SDRAM_CONFIGURATION, CFG_SDRAM_CONFIG);
222
223        /* ----- DEVICE BUS SETTINGS ------ */
224
225        /*
226         * EVB
227         * 0 - SRAM
228         * 1 - RTC
229         * 2 - UART
230         * 3 - Flash
231         * boot - BootCS
232         *
233         * Zuma
234         * 0 - Flash
235         * boot - BootCS
236         */
237
238        /*
239         * the dual 7450 module requires burst access to the boot
240         * device, so the serial rom copies the boot device to the
241         * on-board sram on the eval board, and updates the correct
242         * registers to boot from the sram. (device0)
243         */
244#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4)
245        /* Zuma has no SRAM */
246        sram_boot = 0;
247#else
248        if (memoryGetDeviceBaseAddress(DEVICE0) && 0xfff00000 == CFG_MONITOR_BASE)
249                sram_boot = 1;
250#endif
251
252                memoryMapDeviceSpace(DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
253
254        memoryMapDeviceSpace(DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
255        memoryMapDeviceSpace(DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
256        memoryMapDeviceSpace(DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
257
258        /* configure device timing */
259#ifdef CFG_DEV0_PAR
260        if (!sram_boot)
261                GT_REG_WRITE(DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
262#endif
263
264#ifdef CFG_DEV1_PAR
265        GT_REG_WRITE(DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
266#endif
267#ifdef CFG_DEV2_PAR
268        GT_REG_WRITE(DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
269#endif
270
271#ifdef CONFIG_EVB64260
272#ifdef CFG_32BIT_BOOT_PAR
273        /* detect if we are booting from the 32 bit flash */
274        if (GTREGREAD(DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
275                /* 32 bit boot flash */
276                GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
277                GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_32BIT_BOOT_PAR);
278        } else {
279                /* 8 bit boot flash */
280                GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
281                GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
282        }
283#else
284        /* 8 bit boot flash only */
285        GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
286#endif
287#else /* CONFIG_EVB64260 not defined */
288                /* We are booting from 16-bit flash.
289                 */
290        GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_16BIT_BOOT_PAR);
291#endif
292
293        gt_cpu_config();
294
295        /* MPP setup */
296        GT_REG_WRITE(MPP_CONTROL0, CFG_MPP_CONTROL_0);
297        GT_REG_WRITE(MPP_CONTROL1, CFG_MPP_CONTROL_1);
298        GT_REG_WRITE(MPP_CONTROL2, CFG_MPP_CONTROL_2);
299        GT_REG_WRITE(MPP_CONTROL3, CFG_MPP_CONTROL_3);
300
301        GT_REG_WRITE(GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
302        GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, CFG_SERIAL_PORT_MUX);
303
304        return 0;
305}
306
307/* various things to do after relocation */
308
309int misc_init_r (void)
310{
311        icache_enable();
312#ifdef CFG_L2
313        l2cache_enable();
314#endif
315
316#ifdef CONFIG_MPSC
317        mpsc_init2();
318#endif
319
320#ifdef CONFIG_ZUMA_V2
321        zuma_mbox_init();
322#endif
323        return (0);
324}
325
326void
327after_reloc(ulong dest_addr)
328{
329        /* check to see if we booted from the sram.  If so, move things
330         * back to the way they should be. (we're running from main
331         * memory at this point now */
332
333        if (memoryGetDeviceBaseAddress(DEVICE0) == CFG_MONITOR_BASE) {
334                memoryMapDeviceSpace(DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
335                memoryMapDeviceSpace(BOOT_DEVICE, CFG_FLASH_BASE, _1M);
336        }
337
338        /* now, jump to the main U-Boot board init code */
339        board_init_r ((gd_t *)gd, dest_addr);
340
341        /* NOTREACHED */
342}
343
344/* ------------------------------------------------------------------------- */
345
346/*
347 * Check Board Identity:
348 */
349
350int
351checkboard (void)
352{
353        puts ("Board: " CFG_BOARD_NAME "\n");
354        return (0);
355}
356
357/* utility functions */
358void
359debug_led(int led, int mode)
360{
361#if !defined(CONFIG_ZUMA_V2) && !defined(CONFIG_P3G4)
362        volatile int *addr = NULL;
363        int dummy;
364
365        if (mode == 1) {
366                switch (led) {
367                case 0:
368                        addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x08000);
369                        break;
370
371                case 1:
372                        addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x0c000);
373                        break;
374
375                case 2:
376                        addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x10000);
377                        break;
378                }
379        } else if (mode == 0) {
380                switch (led) {
381                case 0:
382                        addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x14000);
383                        break;
384
385                case 1:
386                        addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x18000);
387                        break;
388
389                case 2:
390                        addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x1c000);
391                        break;
392                }
393        }
394        WRITE_CHAR(addr, 0);
395        dummy = *addr;
396#endif /* CONFIG_ZUMA_V2 */
397}
398
399void
400display_mem_map(void)
401{
402    int i,j;
403    unsigned int base,size,width;
404    /* SDRAM */
405    printf("SDRAM\n");
406    for(i=0;i<=BANK3;i++) {
407        base = memoryGetBankBaseAddress(i);
408        size = memoryGetBankSize(i);
409        if(size !=0)
410        {
411            printf("BANK%d: base - 0x%08x\tsize - %dM bytes\n",i,base,size>>20);
412        }
413    }
414
415    /* CPU's PCI windows */
416    for(i=0;i<=PCI_HOST1;i++) {
417        printf("\nCPU's PCI %d windows\n", i);
418        base=pciGetSpaceBase(i,PCI_IO);
419        size=pciGetSpaceSize(i,PCI_IO);
420        printf("      IO: base - 0x%08x\tsize - %dM bytes\n",base,size>>20);
421        for(j=0;j<=PCI_REGION3;j++) {
422            base = pciGetSpaceBase(i,j);
423            size = pciGetSpaceSize(i,j);
424            printf("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n",j,base,
425                    size>>20);
426        }
427    }
428
429    /* Devices */
430    printf("\nDEVICES\n");
431        for(i=0;i<=DEVICE3;i++) {
432        base = memoryGetDeviceBaseAddress(i);
433        size = memoryGetDeviceSize(i);
434        width= memoryGetDeviceWidth(i) * 8;
435        printf("DEV %d:  base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n",
436               i, base, size>>20, width);
437    }
438
439    /* Bootrom */
440    base = memoryGetDeviceBaseAddress(BOOT_DEVICE); /* Boot */
441    size = memoryGetDeviceSize(BOOT_DEVICE);
442    width= memoryGetDeviceWidth(BOOT_DEVICE) * 8;
443    printf(" BOOT:  base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n",
444           base, size>>20, width);
445}
446
447int board_eth_init(bd_t *bis)
448{
449        gt6426x_eth_initialize(bis);
450        return 0;
451}
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