| 1 | #include <config.h> |
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| 2 | #include <74xx_7xx.h> |
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| 3 | #include <version.h> |
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| 4 | |
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| 5 | #include <ppc_asm.tmpl> |
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| 6 | #include <ppc_defs.h> |
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| 7 | |
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| 8 | #include <asm/cache.h> |
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| 9 | #include <asm/mmu.h> |
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| 10 | |
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| 11 | #include <galileo/gt64260R.h> |
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| 12 | |
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| 13 | #ifdef CONFIG_ECC |
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| 14 | /* Galileo specific asm code for initializing ECC */ |
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| 15 | .globl board_relocate_rom |
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| 16 | board_relocate_rom: |
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| 17 | mflr r7 |
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| 18 | /* update the location of the GT registers */ |
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| 19 | lis r11, CFG_GT_REGS@h |
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| 20 | /* if we're using ECC, we must use the DMA engine to copy ourselves */ |
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| 21 | bl start_idma_transfer_0 |
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| 22 | bl wait_for_idma_0 |
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| 23 | bl stop_idma_engine_0 |
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| 24 | |
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| 25 | mtlr r7 |
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| 26 | blr |
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| 27 | |
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| 28 | .globl board_init_ecc |
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| 29 | board_init_ecc: |
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| 30 | mflr r7 |
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| 31 | /* NOTE: r10 still contains the location we've been relocated to |
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| 32 | * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */ |
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| 33 | |
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| 34 | /* now that we're running from ram, init the rest of main memory |
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| 35 | * for ECC use */ |
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| 36 | lis r8, CFG_MONITOR_LEN@h |
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| 37 | ori r8, r8, CFG_MONITOR_LEN@l |
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| 38 | |
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| 39 | divw r3, r10, r8 |
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| 40 | |
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| 41 | /* set up the counter, and init the starting address */ |
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| 42 | mtctr r3 |
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| 43 | li r12, 0 |
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| 44 | |
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| 45 | /* bytes per transfer */ |
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| 46 | mr r5, r8 |
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| 47 | about_to_init_ecc: |
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| 48 | 1: mr r3, r12 |
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| 49 | mr r4, r12 |
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| 50 | bl start_idma_transfer_0 |
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| 51 | bl wait_for_idma_0 |
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| 52 | bl stop_idma_engine_0 |
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| 53 | add r12, r12, r8 |
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| 54 | bdnz 1b |
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| 55 | |
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| 56 | mtlr r7 |
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| 57 | blr |
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| 58 | |
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| 59 | /* r3: dest addr |
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| 60 | * r4: source addr |
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| 61 | * r5: byte count |
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| 62 | * r11: gt regbase |
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| 63 | * trashes: r6, r5 |
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| 64 | */ |
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| 65 | start_idma_transfer_0: |
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| 66 | /* set the byte count, including the OWN bit */ |
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| 67 | mr r6, r11 |
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| 68 | ori r6, r6, CHANNEL0_DMA_BYTE_COUNT |
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| 69 | stwbrx r5, 0, (r6) |
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| 70 | |
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| 71 | /* set the source address */ |
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| 72 | mr r6, r11 |
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| 73 | ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS |
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| 74 | stwbrx r4, 0, (r6) |
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| 75 | |
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| 76 | /* set the dest address */ |
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| 77 | mr r6, r11 |
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| 78 | ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS |
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| 79 | stwbrx r3, 0, (r6) |
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| 80 | |
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| 81 | /* set the next record pointer */ |
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| 82 | li r5, 0 |
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| 83 | mr r6, r11 |
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| 84 | ori r6, r6, CHANNEL0NEXT_RECORD_POINTER |
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| 85 | stwbrx r5, 0, (r6) |
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| 86 | |
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| 87 | /* set the low control register */ |
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| 88 | /* bit 9 is NON chained mode, bit 31 is new style descriptors. |
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| 89 | bit 12 is channel enable */ |
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| 90 | ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11) |
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| 91 | /* 15 shifted by 16 (oris) == bit 31 */ |
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| 92 | oris r5, r5, (1 << 15) |
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| 93 | mr r6, r11 |
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| 94 | ori r6, r6, CHANNEL0CONTROL |
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| 95 | stwbrx r5, 0, (r6) |
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| 96 | |
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| 97 | blr |
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| 98 | |
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| 99 | /* this waits for the bytecount to return to zero, indicating |
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| 100 | * that the trasfer is complete */ |
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| 101 | wait_for_idma_0: |
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| 102 | mr r5, r11 |
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| 103 | lis r6, 0xff |
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| 104 | ori r6, r6, 0xffff |
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| 105 | ori r5, r5, CHANNEL0_DMA_BYTE_COUNT |
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| 106 | 1: lwbrx r4, 0, (r5) |
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| 107 | and. r4, r4, r6 |
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| 108 | bne 1b |
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| 109 | |
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| 110 | blr |
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| 111 | |
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| 112 | /* this turns off channel 0 of the idma engine */ |
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| 113 | stop_idma_engine_0: |
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| 114 | /* shut off the DMA engine */ |
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| 115 | li r5, 0 |
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| 116 | mr r6, r11 |
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| 117 | ori r6, r6, CHANNEL0CONTROL |
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| 118 | stwbrx r5, 0, (r6) |
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| 119 | |
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| 120 | blr |
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| 121 | #endif |
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| 122 | |
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| 123 | #ifdef CFG_BOARD_ASM_INIT |
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| 124 | /* NOTE: trashes r3-r7 */ |
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| 125 | .globl board_asm_init |
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| 126 | board_asm_init: |
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| 127 | /* just move the GT registers to where they belong */ |
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| 128 | lis r3, CFG_DFL_GT_REGS@h |
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| 129 | ori r3, r3, CFG_DFL_GT_REGS@l |
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| 130 | lis r4, CFG_GT_REGS@h |
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| 131 | ori r4, r4, CFG_GT_REGS@l |
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| 132 | li r5, INTERNAL_SPACE_DECODE |
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| 133 | |
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| 134 | /* test to see if we've already moved */ |
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| 135 | lwbrx r6, r5, r4 |
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| 136 | andi. r6, r6, 0xffff |
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| 137 | rlwinm r7, r4, 12, 16, 31 |
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| 138 | cmp cr0, r7, r6 |
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| 139 | beqlr |
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| 140 | |
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| 141 | /* nope, have to move the registers */ |
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| 142 | lwbrx r6, r5, r3 |
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| 143 | andis. r6, r6, 0xffff |
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| 144 | or r6, r6, r7 |
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| 145 | stwbrx r6, r5, r3 |
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| 146 | |
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| 147 | /* now, poll for the change */ |
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| 148 | 1: lwbrx r7, r5, r4 |
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| 149 | cmp cr0, r7, r6 |
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| 150 | bne 1b |
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| 151 | |
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| 152 | /* done! */ |
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| 153 | blr |
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| 154 | #endif |
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| 155 | |
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| 156 | /* For use of the debug LEDs */ |
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| 157 | .global led_on0 |
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| 158 | led_on0: |
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| 159 | xor r18, r18, r18 |
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| 160 | lis r18, 0x1c80 |
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| 161 | ori r18, r18, 0x8000 |
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| 162 | stw r18, 0x0(r18) |
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| 163 | sync |
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| 164 | blr |
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| 165 | |
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| 166 | .global led_on1 |
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| 167 | led_on1: |
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| 168 | xor r18, r18, r18 |
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| 169 | lis r18, 0x1c80 |
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| 170 | ori r18, r18, 0xc000 |
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| 171 | stw r18, 0x0(r18) |
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| 172 | sync |
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| 173 | blr |
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| 174 | |
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| 175 | .global led_on2 |
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| 176 | led_on2: |
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| 177 | xor r18, r18, r18 |
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| 178 | lis r18, 0x1c81 |
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| 179 | ori r18, r18, 0x0000 |
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| 180 | stw r18, 0x0(r18) |
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| 181 | sync |
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| 182 | blr |
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