source: SVN/rincon/u-boot/board/freescale/m5235evb/m5235evb.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 2 years ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 3.1 KB
Line 
1/*
2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <config.h>
28#include <common.h>
29#include <asm/immap.h>
30
31DECLARE_GLOBAL_DATA_PTR;
32
33int checkboard(void)
34{
35        puts("Board: ");
36        puts("Freescale M5235 EVB\n");
37        return 0;
38};
39
40phys_size_t initdram(int board_type)
41{
42        volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
43        volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
44        u32 dramsize, i, dramclk;
45
46        /*
47         * When booting from external Flash, the port-size is less than
48         * the port-size of SDRAM.  In this case it is necessary to enable
49         * Data[15:0] on Port Address/Data.
50         */
51        gpio->par_ad =
52            GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
53            GPIO_PAR_AD_DATAL;
54
55        /* Initialize PAR to enable SDRAM signals */
56        gpio->par_sdram =
57            GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | GPIO_PAR_SDRAM_SRAS |
58            GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3);
59
60        dramsize = CFG_SDRAM_SIZE * 0x100000;
61        for (i = 0x13; i < 0x20; i++) {
62                if (dramsize == (1 << i))
63                        break;
64        }
65        i--;
66
67        if (!(sdram->dacr0 & SDRAMC_DARCn_RE)) {
68                dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ);
69
70                /* Initialize DRAM Control Register: DCR */
71                sdram->dcr = SDRAMC_DCR_RTIM_9CLKS |
72                    SDRAMC_DCR_RTIM_6CLKS | SDRAMC_DCR_RC((15 * dramclk) >> 4);
73
74                /* Initialize DACR0 */
75                sdram->dacr0 =
76                    SDRAMC_DARCn_BA(CFG_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
77                    SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32;
78                asm("nop");
79
80                /* Initialize DMR0 */
81                sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V;
82                asm("nop");
83
84                /* Set IP (bit 3) in DACR */
85                sdram->dacr0 |= SDRAMC_DARCn_IP;
86
87                /* Wait 30ns to allow banks to precharge */
88                for (i = 0; i < 5; i++) {
89                        asm("nop");
90                }
91
92                /* Write to this block to initiate precharge */
93                *(u32 *) (CFG_SDRAM_BASE) = 0xA5A59696;
94
95                /*  Set RE (bit 15) in DACR */
96                sdram->dacr0 |= SDRAMC_DARCn_RE;
97
98                /* Wait for at least 8 auto refresh cycles to occur */
99                for (i = 0; i < 0x2000; i++) {
100                        asm("nop");
101                }
102
103                /* Finish the configuration by issuing the MRS. */
104                sdram->dacr0 |= SDRAMC_DARCn_IMRS;
105                asm("nop");
106
107                /* Write to the SDRAM Mode Register */
108                *(u32 *) (CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
109        }
110
111        return dramsize;
112};
113
114int testdram(void)
115{
116        /* TODO: XXX XXX XXX */
117        printf("DRAM test not implemented!\n");
118
119        return (0);
120}
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