1 | /* |
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2 | * (C) Copyright 2004-05; Tundra Semiconductor Corp. |
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3 | * |
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4 | * Added automatic detect of SDC settings |
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5 | * Copyright (c) 2005 Freescale Semiconductor, Inc. |
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6 | * Maintainer tie-fei.zang@freescale.com |
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7 | * |
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8 | * This program is free software; you can redistribute it and/or |
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9 | * modify it under the terms of the GNU General Public License as |
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10 | * published by the Free Software Foundation; either version 2 of |
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11 | * the License, or (at your option) any later version. |
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12 | * |
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13 | * This program is distributed in the hope that it will be useful, |
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14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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16 | * GNU General Public License for more details. |
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17 | * |
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18 | * You should have received a copy of the GNU General Public License |
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19 | * along with this program; if not, write to the Free Software |
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20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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21 | * MA 02111-1307 USA |
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22 | */ |
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23 | |
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24 | /* |
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25 | * FILENAME: asm_init.s |
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26 | * |
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27 | * Originator: Alex Bounine |
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28 | * |
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29 | * DESCRIPTION: |
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30 | * Initialization code for the Tundra Tsi108 bridge chip |
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31 | * |
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32 | */ |
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33 | |
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34 | #include <config.h> |
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35 | #include <version.h> |
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36 | |
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37 | #include <ppc_asm.tmpl> |
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38 | #include <ppc_defs.h> |
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39 | #include <asm/processor.h> |
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40 | |
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41 | #include <tsi108.h> |
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42 | |
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43 | /* |
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44 | * Build Configuration Options |
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45 | */ |
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46 | |
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47 | /* #define DISABLE_PBM disables usage of PB Master */ |
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48 | /* #define SDC_HARDCODED_INIT config SDRAM controller with hardcoded values */ |
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49 | /* #define SDC_AUTOPRECH_EN enable SDRAM auto precharge */ |
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50 | |
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51 | /* |
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52 | * Hardcoded SDC settings |
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53 | */ |
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54 | |
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55 | #ifdef SDC_HARDCODED_INIT |
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56 | |
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57 | /* Micron MT9HTF6472AY-40EA1 : Unbuffered, 512MB, 400, CL3, Single Rank */ |
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58 | |
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59 | #define VAL_SD_REFRESH (0x61A) |
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60 | #define VAL_SD_TIMING (0x0308336b) |
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61 | #define VAL_SD_D0_CTRL (0x07100021) /* auto-precharge disabled */ |
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62 | #define VAL_SD_D0_BAR (0x0FE00000) /* 512MB @ 0x00000000 */ |
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63 | #define VAL_SD_D1_CTRL (0x07100021) /* auto-precharge disabled */ |
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64 | #define VAL_SD_D1_BAR (0x0FE00200) /* 512MB @ 0x20000000 */ |
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65 | |
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66 | #endif /* SDC_HARDCODED_INIT */ |
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67 | |
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68 | /* |
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69 | CPU Configuration: |
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70 | |
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71 | CPU Address and Data Parity enables. |
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72 | |
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73 | #define CPU_AP |
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74 | #define CPU_DP |
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75 | */ |
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76 | |
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77 | /* |
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78 | * Macros |
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79 | * !!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are |
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80 | * expected to work correctly for the CSR space within 32KB range. |
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81 | * |
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82 | * LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant. |
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83 | * These macros are absolutely identical except their names. This difference |
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84 | * is provided intentionally for better readable code. |
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85 | */ |
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86 | |
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87 | #define LOAD_PTR(reg,const32) \ |
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88 | addis reg,r0,const32@h; ori reg,reg,const32@l |
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89 | |
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90 | #define LOAD_U32(reg,const32) \ |
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91 | addis reg,r0,const32@h; ori reg,reg,const32@l |
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92 | |
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93 | /* LOADMEM initializes a register with the contents of a specified 32-bit |
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94 | * memory location, usually a CSR value. |
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95 | */ |
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96 | |
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97 | #define LOAD_MEM(reg,addr32) \ |
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98 | addis reg,r0,addr32@ha; lwz reg,addr32@l(reg) |
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99 | |
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100 | #ifndef SDC_HARDCODED_INIT |
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101 | sdc_clk_sync: |
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102 | /* MHz: 0,0,183,100,133,167,200,233 */ |
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103 | .long 0, 0, 6, 10, 8, 6, 5, 4 /* nSec */ |
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104 | #endif |
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105 | |
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106 | /* |
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107 | * board_asm_init() - early initialization function. Coded to be portable to |
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108 | * dual-CPU configuration. |
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109 | * Checks CPU number and performs board HW initialization if called for CPU0. |
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110 | * Registers used: r3,r4,r5,r6,r19,r29 |
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111 | * |
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112 | * NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108 |
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113 | * and the rest of the board. Current implementation demonstrates two |
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114 | * possible ways to identify CPU number: |
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115 | * - for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM. |
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116 | * - for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108. |
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117 | */ |
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118 | |
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119 | .globl board_asm_init |
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120 | board_asm_init: |
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121 | mflr r19 /* Save LR to be able return later. */ |
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122 | bl icache_enable /* Enable icache to reduce reads from flash. */ |
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123 | |
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124 | /* Initialize pointer to Tsi108 register space */ |
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125 | |
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126 | LOAD_PTR(r29,CFG_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */ |
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127 | ori r4,r29,TSI108_PB_REG_OFFSET |
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128 | |
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129 | /* Check Processor Version Number */ |
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130 | |
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131 | mfspr r3, PVR |
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132 | rlwinm r3,r3,16,16,23 /* get ((Processor Version Number) & 0xFF00) */ |
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133 | |
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134 | cmpli 0,0,r3,0x8000 /* MPC74xx */ |
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135 | bne cont_brd_init |
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136 | |
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137 | /* |
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138 | * For MPC744x/5x enable extended BATs[4-7] |
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139 | * Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1 |
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140 | * to disable prefetch |
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141 | */ |
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142 | |
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143 | mfspr r5, HID0 |
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144 | oris r5, r5, 0x0080 /* Set HID0[HIGH_BAT_EN] bit #8 */ |
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145 | ori r5, r5, 0x0380 /* Set SPD,XBSEN,SGE bits #22,23,24 */ |
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146 | mtspr HID0, r5 |
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147 | isync |
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148 | sync |
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149 | |
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150 | /* Adding code to disable external interventions in MPX bus mode */ |
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151 | mfspr r3, 1014 |
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152 | oris r3, r3, 0x0100 /* Set the EIDIS bit in MSSCR0: bit 7 */ |
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153 | mtspr 1014, r3 |
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154 | isync |
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155 | sync |
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156 | |
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157 | /* Sri: code to enable FP unit */ |
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158 | mfmsr r3 |
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159 | ori r3, r3, 0x2000 |
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160 | mtmsr r3 |
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161 | isync |
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162 | sync |
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163 | |
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164 | /* def CONFIG_DUAL_CPU |
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165 | * For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number. |
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166 | */ |
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167 | #if(1) |
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168 | mfspr r3,1014 /* read MSSCR0 */ |
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169 | rlwinm. r3,r3,27,31,31 /* get processor ID number */ |
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170 | mtspr SPRN_PIR,r3 /* Save CPU ID */ |
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171 | sync |
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172 | bne init_done |
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173 | b do_tsi108_init |
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174 | |
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175 | cont_brd_init: |
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176 | |
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177 | /* An alternative method of checking the processor number (in addition |
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178 | * to configuration using MSSCR0[ID] bit on MPC74xx). |
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179 | * Good for IBM PPC750FX/GX. |
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180 | */ |
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181 | |
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182 | lwz r3,PB_BUS_MS_SELECT(r4) /* read PB_ID register */ |
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183 | rlwinm. r3,r3,24,31,31 /* get processor ID number */ |
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184 | bne init_done |
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185 | #else |
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186 | |
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187 | cont_brd_init: |
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188 | |
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189 | #endif /* CONFIG_DUAL_CPU */ |
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190 | |
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191 | /* Initialize Tsi108 chip */ |
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192 | |
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193 | do_tsi108_init: |
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194 | |
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195 | /* |
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196 | * Adjust HLP/Flash parameters. By default after reset the HLP port is |
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197 | * set to support slow devices. Better performance can be achived when |
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198 | * an optimal parameters are used for specific EPROM device. |
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199 | * NOTE: This should be performed ASAP for the emulation platform |
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200 | * because it has 5MHz HLP clocking. |
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201 | */ |
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202 | |
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203 | #ifdef CONFIG_TSI108EMU |
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204 | ori r4,r29,TSI108_HLP_REG_OFFSET |
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205 | LOAD_U32(r5,0x434422c0) |
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206 | stw r5,0x08(r4) /* set HLP B0_CTRL0 */ |
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207 | sync |
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208 | LOAD_U32(r5,0xd0012000) |
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209 | stw r5,0x0c(r4) /* set HLP B0_CTRL1 */ |
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210 | sync |
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211 | #endif |
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212 | |
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213 | /* Initialize PB interface. */ |
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214 | |
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215 | ori r4,r29,TSI108_PB_REG_OFFSET |
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216 | |
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217 | #if (CFG_TSI108_CSR_BASE != CFG_TSI108_CSR_RST_BASE) |
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218 | /* Relocate (if required) Tsi108 registers. Set new value for |
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219 | * PB_REG_BAR: |
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220 | * Note we are in the 32-bit address mode. |
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221 | */ |
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222 | LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */ |
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223 | stw r5,PB_REG_BAR(r4) |
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224 | andis. r29,r5,0xFFFF |
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225 | sync |
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226 | ori r4,r29,TSI108_PB_REG_OFFSET |
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227 | #endif |
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228 | |
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229 | /* Set PB Slave configuration register */ |
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230 | |
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231 | LOAD_U32(r5,0x00002481) /* PB_SCR: TEA enabled,AACK delay = 1 */ |
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232 | lwz r3, PB_RSR(r4) /* get PB bus mode */ |
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233 | xori r3,r3,0x0001 /* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */ |
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234 | rlwimi r5,r3,14,17,17 /* for MPX: set DTI_MODE bit */ |
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235 | stw r5,PB_SCR(r4) |
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236 | sync |
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237 | |
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238 | /* Configure PB Arbiter */ |
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239 | |
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240 | lwz r5,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */ |
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241 | li r3, 0x00F0 /* ARB_PIPELINE_DEP mask */ |
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242 | #ifdef DISABLE_PBM |
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243 | ori r3,r3,0x1000 /* add PBM_EN to clear (enabled by default) */ |
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244 | #endif |
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245 | andc r5,r5,r3 /* Clear the masked bit fields */ |
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246 | ori r5,r5,0x0001 /* Set pipeline depth */ |
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247 | stw r5,PB_ARB_CTRL(r4) |
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248 | |
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249 | #if (0) /* currently using the default settings for PBM after reset */ |
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250 | LOAD_U32(r5,0x) /* value for PB_MCR */ |
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251 | stw r5,PB_MCR(r4) |
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252 | sync |
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253 | |
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254 | LOAD_U32(r5,0x) /* value for PB_MCMD */ |
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255 | stw r5,PB_MCMD(r4) |
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256 | sync |
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257 | #endif |
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258 | |
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259 | /* Disable or enable PVT based on processor bus frequency |
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260 | * 1. Read CG_PWRUP_STATUS register field bits 18,17,16 |
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261 | * 2. See if the value is < or > 133mhz (18:16 = 100) |
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262 | * 3. If > enable PVT |
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263 | */ |
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264 | |
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265 | LOAD_U32(r3,0xC0002234) |
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266 | lwz r3,0(r3) |
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267 | rlwinm r3,r3,16,29,31 |
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268 | |
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269 | cmpi 0,0,r3,0x0004 |
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270 | bgt sdc_init |
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271 | |
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272 | #ifndef CONFIG_TSI108EMU |
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273 | /* FIXME: Disable PB calibration control for any real Tsi108 board */ |
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274 | li r5,0x0101 /* disable calibration control */ |
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275 | stw r5,PB_PVT_CTRL2(r4) |
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276 | sync |
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277 | #endif |
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278 | |
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279 | /* Initialize SDRAM controller. */ |
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280 | |
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281 | sdc_init: |
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282 | |
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283 | #ifndef SDC_HARDCODED_INIT |
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284 | /* get SDC clock prior doing sdram controller autoconfig */ |
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285 | ori r4,r29,TSI108_CLK_REG_OFFSET /* r4 - ptr to CG registers */ |
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286 | lwz r3, CG_PWRUP_STATUS(r4) /* get CG configuration */ |
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287 | rlwinm r3,r3,12,29,31 /* r3 - SD clk */ |
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288 | lis r5,sdc_clk_sync@h |
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289 | ori r5,r5,sdc_clk_sync@l |
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290 | /* Sri: At this point check if r3 = 001. If yes, |
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291 | * the memory frequency should be same as the |
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292 | * MPX bus frequency |
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293 | */ |
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294 | cmpi 0,0,r3,0x0001 |
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295 | bne get_nsec |
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296 | lwz r6, CG_PWRUP_STATUS(r4) |
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297 | rlwinm r6,r6,16,29,31 |
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298 | mr r3,r6 |
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299 | |
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300 | get_nsec: |
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301 | rlwinm r3,r3,2,0,31 |
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302 | lwzx r9,r5,r3 /* get SD clk rate in nSec */ |
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303 | /* ATTN: r9 will be used by SPD routine */ |
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304 | #endif /* !SDC_HARDCODED_INIT */ |
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305 | |
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306 | ori r4,r29,TSI108_SD_REG_OFFSET /* r4 - ptr to SDRAM registers */ |
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307 | |
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308 | /* Initialize SDRAM controller. SDRAM Size = 512MB, One DIMM. */ |
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309 | |
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310 | LOAD_U32(r5,0x00) |
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311 | stw r5,SD_INT_ENABLE(r4) /* Ensure that interrupts are disabled */ |
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312 | #ifdef ENABLE_SDRAM_ECC |
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313 | li r5, 0x01 |
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314 | #endif /* ENABLE_SDRAM_ECC */ |
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315 | stw r5,SD_ECC_CTRL(r4) /* Enable/Disable ECC */ |
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316 | sync |
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317 | |
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318 | #ifdef SDC_HARDCODED_INIT /* config sdram controller with hardcoded values */ |
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319 | |
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320 | /* First read the CG_PWRUP_STATUS register to get the |
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321 | * memory speed from bits 22,21,20 |
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322 | */ |
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323 | |
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324 | LOAD_U32(r3,0xC0002234) |
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325 | lwz r3,0(r3) |
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326 | rlwinm r3,r3,12,29,31 |
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327 | |
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328 | /* Now first check for 166, then 200, or default */ |
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329 | |
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330 | cmpi 0,0,r3,0x0005 |
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331 | bne check_for_200mhz |
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332 | |
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333 | /* set values for 166 Mhz memory speed |
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334 | * Set refresh rate and timing parameters |
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335 | */ |
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336 | LOAD_U32(r5,0x00000515) |
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337 | stw r5,SD_REFRESH(r4) |
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338 | LOAD_U32(r5,0x03073368) |
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339 | stw r5,SD_TIMING(r4) |
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340 | sync |
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341 | |
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342 | /* Initialize DIMM0 control and BAR registers */ |
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343 | LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ |
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344 | #ifdef SDC_AUTOPRECH_EN |
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345 | oris r5,r5,0x0001 /* set auto precharge EN bit */ |
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346 | #endif |
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347 | stw r5,SD_D0_CTRL(r4) |
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348 | LOAD_U32(r5,VAL_SD_D0_BAR) |
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349 | stw r5,SD_D0_BAR(r4) |
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350 | sync |
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351 | |
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352 | /* Initialize DIMM1 control and BAR registers |
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353 | * (same as dimm 0, next 512MB, disabled) |
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354 | */ |
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355 | LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ |
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356 | #ifdef SDC_AUTOPRECH_EN |
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357 | oris r5,r5,0x0001 /* set auto precharge EN bit */ |
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358 | #endif |
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359 | stw r5,SD_D1_CTRL(r4) |
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360 | LOAD_U32(r5,VAL_SD_D1_BAR) |
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361 | stw r5,SD_D1_BAR(r4) |
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362 | sync |
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363 | |
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364 | b sdc_init_done |
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365 | |
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366 | check_for_200mhz: |
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367 | |
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368 | cmpi 0,0,r3,0x0006 |
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369 | bne set_default_values |
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370 | |
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371 | /* set values for 200Mhz memory speed |
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372 | * Set refresh rate and timing parameters |
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373 | */ |
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374 | LOAD_U32(r5,0x0000061a) |
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375 | stw r5,SD_REFRESH(r4) |
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376 | LOAD_U32(r5,0x03083348) |
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377 | stw r5,SD_TIMING(r4) |
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378 | sync |
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379 | |
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380 | /* Initialize DIMM0 control and BAR registers */ |
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381 | LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ |
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382 | #ifdef SDC_AUTOPRECH_EN |
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383 | oris r5,r5,0x0001 /* set auto precharge EN bit */ |
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384 | #endif |
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385 | stw r5,SD_D0_CTRL(r4) |
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386 | LOAD_U32(r5,VAL_SD_D0_BAR) |
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387 | stw r5,SD_D0_BAR(r4) |
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388 | sync |
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389 | |
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390 | /* Initialize DIMM1 control and BAR registers |
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391 | * (same as dimm 0, next 512MB, disabled) |
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392 | */ |
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393 | LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ |
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394 | #ifdef SDC_AUTOPRECH_EN |
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395 | oris r5,r5,0x0001 /* set auto precharge EN bit */ |
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396 | #endif |
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397 | stw r5,SD_D1_CTRL(r4) |
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398 | LOAD_U32(r5,VAL_SD_D1_BAR) |
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399 | stw r5,SD_D1_BAR(r4) |
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400 | sync |
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401 | |
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402 | b sdc_init_done |
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403 | |
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404 | set_default_values: |
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405 | |
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406 | /* Set refresh rate and timing parameters */ |
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407 | LOAD_U32(r5,VAL_SD_REFRESH) |
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408 | stw r5,SD_REFRESH(r4) |
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409 | LOAD_U32(r5,VAL_SD_TIMING) |
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410 | stw r5,SD_TIMING(r4) |
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411 | sync |
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412 | |
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413 | /* Initialize DIMM0 control and BAR registers */ |
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414 | LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ |
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415 | #ifdef SDC_AUTOPRECH_EN |
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416 | oris r5,r5,0x0001 /* set auto precharge EN bit */ |
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417 | #endif |
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418 | stw r5,SD_D0_CTRL(r4) |
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419 | LOAD_U32(r5,VAL_SD_D0_BAR) |
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420 | stw r5,SD_D0_BAR(r4) |
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421 | sync |
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422 | |
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423 | /* Initialize DIMM1 control and BAR registers |
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424 | * (same as dimm 0, next 512MB, disabled) |
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425 | */ |
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426 | LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ |
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427 | #ifdef SDC_AUTOPRECH_EN |
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428 | oris r5,r5,0x0001 /* set auto precharge EN bit */ |
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429 | #endif |
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430 | stw r5,SD_D1_CTRL(r4) |
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431 | LOAD_U32(r5,VAL_SD_D1_BAR) |
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432 | stw r5,SD_D1_BAR(r4) |
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433 | sync |
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434 | #else /* !SDC_HARDCODED_INIT */ |
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435 | bl tsi108_sdram_spd /* automatically detect SDC settings */ |
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436 | #endif /* SDC_HARDCODED_INIT */ |
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437 | |
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438 | sdc_init_done: |
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439 | |
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440 | #ifdef DISABLE_PBM |
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441 | LOAD_U32(r5,0x00000030) /* PB_EN + OCN_EN */ |
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442 | #else |
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443 | LOAD_U32(r5,0x00000230) /* PB_EN + OCN_EN + PB/OCN=80/20 */ |
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444 | #endif /* DISABLE_PBM */ |
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445 | |
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446 | #ifdef CONFIG_TSI108EMU |
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447 | oris r5,r5,0x0010 /* set EMULATION_MODE bit */ |
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448 | #endif |
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449 | |
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450 | stw r5,SD_CTRL(r4) |
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451 | eieio |
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452 | sync |
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453 | |
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454 | /* Enable SDRAM access */ |
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455 | |
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456 | oris r5,r5,0x8000 /* start SDC: set SD_CTRL[ENABLE] bit */ |
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457 | stw r5,SD_CTRL(r4) |
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458 | sync |
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459 | |
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460 | wait_init_complete: |
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461 | lwz r5,SD_STATUS(r4) |
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462 | andi. r5,r5,0x0001 |
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463 | /* wait until SDRAM initialization is complete */ |
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464 | beq wait_init_complete |
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465 | |
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466 | /* Map SDRAM into the processor bus address space */ |
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467 | |
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468 | ori r4,r29,TSI108_PB_REG_OFFSET |
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469 | |
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470 | /* Setup BARs associated with direct path PB<->SDRAM */ |
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471 | |
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472 | /* PB_SDRAM_BAR1: |
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473 | * provides a direct path to the main system memory (cacheable SDRAM) |
---|
474 | */ |
---|
475 | |
---|
476 | /* BA=0,Size=512MB, ENable, No Addr.Translation */ |
---|
477 | LOAD_U32(r5, 0x00000011) |
---|
478 | stw r5,PB_SDRAM_BAR1(r4) |
---|
479 | sync |
---|
480 | |
---|
481 | /* Make sure that PB_SDRAM_BAR1 decoder is set |
---|
482 | * (to allow following immediate read from SDRAM) |
---|
483 | */ |
---|
484 | lwz r5,PB_SDRAM_BAR1(r4) |
---|
485 | sync |
---|
486 | |
---|
487 | /* PB_SDRAM_BAR2: |
---|
488 | * provides non-cacheable alias (via the direct path) to main |
---|
489 | * system memory. |
---|
490 | * Size = 512MB, ENable, Addr.Translation - ON, |
---|
491 | * BA = 0x0_40000000, TA = 0x0_00000000 |
---|
492 | */ |
---|
493 | |
---|
494 | LOAD_U32(r5, 0x40010011) |
---|
495 | stw r5,PB_SDRAM_BAR2(r4) |
---|
496 | sync |
---|
497 | |
---|
498 | /* Make sure that PB_SDRAM_BAR2 decoder is set |
---|
499 | * (to allow following immediate read from SDRAM) |
---|
500 | */ |
---|
501 | lwz r5,PB_SDRAM_BAR2(r4) |
---|
502 | sync |
---|
503 | |
---|
504 | init_done: |
---|
505 | |
---|
506 | /* All done. Restore LR and return. */ |
---|
507 | mtlr r19 |
---|
508 | blr |
---|
509 | |
---|
510 | #if (0) |
---|
511 | /* |
---|
512 | * init_cpu1 |
---|
513 | * This routine enables CPU1 on the dual-processor system. |
---|
514 | * Now there is only one processor in the system |
---|
515 | */ |
---|
516 | |
---|
517 | .global enable_cpu1 |
---|
518 | enable_cpu1: |
---|
519 | |
---|
520 | lis r3,Tsi108_Base@ha /* Get Grendel CSR Base Addr */ |
---|
521 | addi r3,r3,Tsi108_Base@l |
---|
522 | lwz r3,0(r3) /* R3 = CSR Base Addr */ |
---|
523 | ori r4,r3,TSI108_PB_REG_OFFSET |
---|
524 | lwz r3,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */ |
---|
525 | ori r3,r3,0x0200 /* Set M1_EN bit */ |
---|
526 | stw r3,PB_ARB_CTRL(r4) |
---|
527 | |
---|
528 | blr |
---|
529 | #endif |
---|
530 | |
---|
531 | /* |
---|
532 | * enable_EI |
---|
533 | * Enable CPU core external interrupt |
---|
534 | */ |
---|
535 | |
---|
536 | .global enable_EI |
---|
537 | enable_EI: |
---|
538 | mfmsr r3 |
---|
539 | ori r3,r3,0x8000 /* set EE bit */ |
---|
540 | mtmsr r3 |
---|
541 | blr |
---|
542 | |
---|
543 | /* |
---|
544 | * disable_EI |
---|
545 | * Disable CPU core external interrupt |
---|
546 | */ |
---|
547 | |
---|
548 | .global disable_EI |
---|
549 | disable_EI: |
---|
550 | mfmsr r3 |
---|
551 | li r4,-32768 /* aka "li r4,0x8000" */ |
---|
552 | andc r3,r3,r4 /* clear EE bit */ |
---|
553 | mtmsr r3 |
---|
554 | blr |
---|
555 | |
---|
556 | #ifdef ENABLE_SDRAM_ECC |
---|
557 | /* enables SDRAM ECC */ |
---|
558 | |
---|
559 | .global enable_ECC |
---|
560 | enable_ECC: |
---|
561 | ori r4,r29,TSI108_SD_REG_OFFSET |
---|
562 | lwz r3,SD_ECC_CTRL(r4) /* Read SDRAM ECC Control Register */ |
---|
563 | ori r3,r3,0x0001 /* Set ECC_EN bit */ |
---|
564 | stw r3,SD_ECC_CTRL(r4) |
---|
565 | blr |
---|
566 | |
---|
567 | /* |
---|
568 | * clear_ECC_err |
---|
569 | * Clears all pending SDRAM ECC errors |
---|
570 | * (normally after SDRAM scrubbing/initialization) |
---|
571 | */ |
---|
572 | |
---|
573 | .global clear_ECC_err |
---|
574 | clear_ECC_err: |
---|
575 | ori r4,r29,TSI108_SD_REG_OFFSET |
---|
576 | ori r3,r0,0x0030 /* ECC_UE_INT + ECC_CE_INT bits */ |
---|
577 | stw r3,SD_INT_STATUS(r4) |
---|
578 | blr |
---|
579 | |
---|
580 | #endif /* ENABLE_SDRAM_ECC */ |
---|
581 | |
---|
582 | #ifndef SDC_HARDCODED_INIT |
---|
583 | |
---|
584 | /* SDRAM SPD Support */ |
---|
585 | #define SD_I2C_CTRL1 (0x400) |
---|
586 | #define SD_I2C_CTRL2 (0x404) |
---|
587 | #define SD_I2C_RD_DATA (0x408) |
---|
588 | #define SD_I2C_WR_DATA (0x40C) |
---|
589 | |
---|
590 | /* |
---|
591 | * SDRAM SPD Support Macros |
---|
592 | */ |
---|
593 | |
---|
594 | #define SPD_DIMM0 (0x00000100) |
---|
595 | #define SPD_DIMM1 (0x00000200) /* SPD_DIMM1 was 0x00000000 */ |
---|
596 | |
---|
597 | #define SPD_RDIMM (0x01) |
---|
598 | #define SPD_UDIMM (0x02) |
---|
599 | |
---|
600 | #define SPD_CAS_3 0x8 |
---|
601 | #define SPD_CAS_4 0x10 |
---|
602 | #define SPD_CAS_5 0x20 |
---|
603 | |
---|
604 | #define ERR_NO_DIMM_FOUND (0xdb0) |
---|
605 | #define ERR_TRAS_FAIL (0xdb1) |
---|
606 | #define ERR_TRCD_FAIL (0xdb2) |
---|
607 | #define ERR_TRP_FAIL (0xdb3) |
---|
608 | #define ERR_TWR_FAIL (0xdb4) |
---|
609 | #define ERR_UNKNOWN_PART (0xdb5) |
---|
610 | #define ERR_NRANK_INVALID (0xdb6) |
---|
611 | #define ERR_DIMM_SIZE (0xdb7) |
---|
612 | #define ERR_ADDR_MODE (0xdb8) |
---|
613 | #define ERR_RFRSH_RATE (0xdb9) |
---|
614 | #define ERR_DIMM_TYPE (0xdba) |
---|
615 | #define ERR_CL_VALUE (0xdbb) |
---|
616 | #define ERR_TRFC_FAIL (0xdbc) |
---|
617 | |
---|
618 | /* READ_SPD requirements: |
---|
619 | * byte - byte address in SPD device (0 - 255) |
---|
620 | * r3 = will return data read from I2C Byte location |
---|
621 | * r4 - unchanged (SDC base addr) |
---|
622 | * r5 - clobbered in routine (I2C status) |
---|
623 | * r10 - number of DDR slot where first SPD device is detected |
---|
624 | */ |
---|
625 | |
---|
626 | #define READ_SPD(byte_num) \ |
---|
627 | addis r3, 0, byte_num@l; \ |
---|
628 | or r3, r3, r10; \ |
---|
629 | ori r3, r3, 0x0A; \ |
---|
630 | stw r3, SD_I2C_CTRL1(r4); \ |
---|
631 | li r3, I2C_CNTRL2_START; \ |
---|
632 | stw r3, SD_I2C_CTRL2(r4); \ |
---|
633 | eieio; \ |
---|
634 | sync; \ |
---|
635 | li r3, 0x100; \ |
---|
636 | 1:; \ |
---|
637 | addic. r3, r3, -1; \ |
---|
638 | bne 1b; \ |
---|
639 | 2:; \ |
---|
640 | lwz r5, SD_I2C_CTRL2(r4); \ |
---|
641 | rlwinm. r3,r5,0,23,23; \ |
---|
642 | bne 2b; \ |
---|
643 | rlwinm. r3,r5,0,3,3; \ |
---|
644 | lwz r3,SD_I2C_RD_DATA(r4) |
---|
645 | |
---|
646 | #define SPD_MIN_RFRSH (0x80) |
---|
647 | #define SPD_MAX_RFRSH (0x85) |
---|
648 | |
---|
649 | refresh_rates: /* in nSec */ |
---|
650 | .long 15625 /* Normal (0x80) */ |
---|
651 | .long 3900 /* Reduced 0.25x (0x81) */ |
---|
652 | .long 7800 /* Reduced 0.5x (0x82) */ |
---|
653 | .long 31300 /* Extended 2x (0x83) */ |
---|
654 | .long 62500 /* Extended 4x (0x84) */ |
---|
655 | .long 125000 /* Extended 8x (0x85) */ |
---|
656 | |
---|
657 | /* |
---|
658 | * tsi108_sdram_spd |
---|
659 | * |
---|
660 | * Inittializes SDRAM Controller using DDR2 DIMM Serial Presence Detect data |
---|
661 | * Uses registers: r4 - SDC base address (not changed) |
---|
662 | * r9 - SDC clocking period in nSec |
---|
663 | * Changes registers: r3,r5,r6,r7,r8,r10,r11 |
---|
664 | */ |
---|
665 | |
---|
666 | tsi108_sdram_spd: |
---|
667 | |
---|
668 | li r10,SPD_DIMM0 |
---|
669 | xor r11,r11,r11 /* DIMM Base Address: starts from 0 */ |
---|
670 | |
---|
671 | do_first_dimm: |
---|
672 | |
---|
673 | /* Program Refresh Rate Register */ |
---|
674 | |
---|
675 | READ_SPD(12) /* get Refresh Rate */ |
---|
676 | beq check_next_slot |
---|
677 | li r5, ERR_RFRSH_RATE |
---|
678 | cmpi 0,0,r3,SPD_MIN_RFRSH |
---|
679 | ble spd_fail |
---|
680 | cmpi 0,0,r3,SPD_MAX_RFRSH |
---|
681 | bgt spd_fail |
---|
682 | addi r3,r3,-SPD_MIN_RFRSH |
---|
683 | rlwinm r3,r3,2,0,31 |
---|
684 | lis r5,refresh_rates@h |
---|
685 | ori r5,r5,refresh_rates@l |
---|
686 | lwzx r5,r5,r3 /* get refresh rate in nSec */ |
---|
687 | divwu r5,r5,r9 /* calculate # of SDC clocks */ |
---|
688 | stw r5,SD_REFRESH(r4) /* Set refresh rate */ |
---|
689 | sync |
---|
690 | |
---|
691 | /* Program SD Timing Register */ |
---|
692 | |
---|
693 | li r7, 0 /* clear r7 prior parameter collection */ |
---|
694 | |
---|
695 | READ_SPD(20) /* get DIMM type: Registered or Unbuffered */ |
---|
696 | beq spd_read_fail |
---|
697 | li r5, ERR_DIMM_TYPE |
---|
698 | cmpi 0,0,r3,SPD_UDIMM |
---|
699 | beq do_cl |
---|
700 | cmpi 0,0,r3,SPD_RDIMM |
---|
701 | bne spd_fail |
---|
702 | oris r7,r7,0x1000 /* set SD_TIMING[DIMM_TYPE] bit */ |
---|
703 | |
---|
704 | do_cl: |
---|
705 | READ_SPD(18) /* Get CAS Latency */ |
---|
706 | beq spd_read_fail |
---|
707 | li r5,ERR_CL_VALUE |
---|
708 | andi. r6,r3,SPD_CAS_3 |
---|
709 | beq cl_4 |
---|
710 | li r6,3 |
---|
711 | b set_cl |
---|
712 | cl_4: |
---|
713 | andi. r6,r3,SPD_CAS_4 |
---|
714 | beq cl_5 |
---|
715 | li r6,4 |
---|
716 | b set_cl |
---|
717 | cl_5: |
---|
718 | andi. r6,r3,SPD_CAS_5 |
---|
719 | beq spd_fail |
---|
720 | li r6,5 |
---|
721 | set_cl: |
---|
722 | rlwimi r7,r6,24,5,7 |
---|
723 | |
---|
724 | READ_SPD(30) /* Get tRAS */ |
---|
725 | beq spd_read_fail |
---|
726 | divwu r6,r3,r9 |
---|
727 | mullw r8,r6,r9 |
---|
728 | subf. r8,r8,r3 |
---|
729 | beq set_tras |
---|
730 | addi r6,r6,1 |
---|
731 | set_tras: |
---|
732 | li r5,ERR_TRAS_FAIL |
---|
733 | cmpi 0,0,r6,0x0F /* max supported value */ |
---|
734 | bgt spd_fail |
---|
735 | rlwimi r7,r6,16,12,15 |
---|
736 | |
---|
737 | READ_SPD(29) /* Get tRCD */ |
---|
738 | beq spd_read_fail |
---|
739 | /* right shift tRCD by 2 bits as per DDR2 spec */ |
---|
740 | rlwinm r3,r3,30,2,31 |
---|
741 | divwu r6,r3,r9 |
---|
742 | mullw r8,r6,r9 |
---|
743 | subf. r8,r8,r3 |
---|
744 | beq set_trcd |
---|
745 | addi r6,r6,1 |
---|
746 | set_trcd: |
---|
747 | li r5,ERR_TRCD_FAIL |
---|
748 | cmpi 0,0,r6,0x07 /* max supported value */ |
---|
749 | bgt spd_fail |
---|
750 | rlwimi r7,r6,12,17,19 |
---|
751 | |
---|
752 | READ_SPD(27) /* Get tRP value */ |
---|
753 | beq spd_read_fail |
---|
754 | rlwinm r3,r3,30,2,31 /* right shift tRP by 2 bits as per DDR2 spec */ |
---|
755 | divwu r6,r3,r9 |
---|
756 | mullw r8,r6,r9 |
---|
757 | subf. r8,r8,r3 |
---|
758 | beq set_trp |
---|
759 | addi r6,r6,1 |
---|
760 | set_trp: |
---|
761 | li r5,ERR_TRP_FAIL |
---|
762 | cmpi 0,0,r6,0x07 /* max supported value */ |
---|
763 | bgt spd_fail |
---|
764 | rlwimi r7,r6,8,21,23 |
---|
765 | |
---|
766 | READ_SPD(36) /* Get tWR value */ |
---|
767 | beq spd_read_fail |
---|
768 | rlwinm r3,r3,30,2,31 /* right shift tWR by 2 bits as per DDR2 spec */ |
---|
769 | divwu r6,r3,r9 |
---|
770 | mullw r8,r6,r9 |
---|
771 | subf. r8,r8,r3 |
---|
772 | beq set_twr |
---|
773 | addi r6,r6,1 |
---|
774 | set_twr: |
---|
775 | addi r6,r6,-1 /* Tsi108 SDC always gives one extra clock */ |
---|
776 | li r5,ERR_TWR_FAIL |
---|
777 | cmpi 0,0,r6,0x07 /* max supported value */ |
---|
778 | bgt spd_fail |
---|
779 | rlwimi r7,r6,5,24,26 |
---|
780 | |
---|
781 | READ_SPD(42) /* Get tRFC */ |
---|
782 | beq spd_read_fail |
---|
783 | li r5, ERR_TRFC_FAIL |
---|
784 | /* Tsi108 spec: tRFC=(tRFC + 1)/2 */ |
---|
785 | addi r3,r3,1 |
---|
786 | rlwinm. r3,r3,31,1,31 /* divide by 2 */ |
---|
787 | beq spd_fail |
---|
788 | divwu r6,r3,r9 |
---|
789 | mullw r8,r6,r9 |
---|
790 | subf. r8,r8,r3 |
---|
791 | beq set_trfc |
---|
792 | addi r6,r6,1 |
---|
793 | set_trfc: |
---|
794 | cmpi 0,0,r6,0x1F /* max supported value */ |
---|
795 | bgt spd_fail |
---|
796 | rlwimi r7,r6,0,27,31 |
---|
797 | |
---|
798 | stw r7,SD_TIMING(r4) |
---|
799 | sync |
---|
800 | |
---|
801 | /* |
---|
802 | * The following two registers are set on per-DIMM basis. |
---|
803 | * The SD_REFRESH and SD_TIMING settings are common for both DIMMS |
---|
804 | */ |
---|
805 | |
---|
806 | do_each_dimm: |
---|
807 | |
---|
808 | /* Program SDRAM DIMM Control Register */ |
---|
809 | |
---|
810 | li r7, 0 /* clear r7 prior parameter collection */ |
---|
811 | |
---|
812 | READ_SPD(13) /* Get Primary SDRAM Width */ |
---|
813 | beq spd_read_fail |
---|
814 | cmpi 0,0,r3,4 /* Check for 4-bit SDRAM */ |
---|
815 | beq do_nbank |
---|
816 | oris r7,r7,0x0010 /* Set MEM_WIDTH bit */ |
---|
817 | |
---|
818 | do_nbank: |
---|
819 | READ_SPD(17) /* Get Number of banks on SDRAM device */ |
---|
820 | beq spd_read_fail |
---|
821 | /* Grendel only distinguish betw. 4 or 8-bank memory parts */ |
---|
822 | li r5,ERR_UNKNOWN_PART /* non-supported memory part */ |
---|
823 | cmpi 0,0,r3,4 |
---|
824 | beq do_nrank |
---|
825 | cmpi 0,0,r3,8 |
---|
826 | bne spd_fail |
---|
827 | ori r7,r7,0x1000 |
---|
828 | |
---|
829 | do_nrank: |
---|
830 | READ_SPD(5) /* Get # of Ranks */ |
---|
831 | beq spd_read_fail |
---|
832 | li r5,ERR_NRANK_INVALID |
---|
833 | andi. r6,r3,0x7 /* Use bits [2..0] only */ |
---|
834 | beq do_addr_mode |
---|
835 | cmpi 0,0,r6,1 |
---|
836 | bgt spd_fail |
---|
837 | rlwimi r7,r6,8,23,23 |
---|
838 | |
---|
839 | do_addr_mode: |
---|
840 | READ_SPD(4) /* Get # of Column Addresses */ |
---|
841 | beq spd_read_fail |
---|
842 | li r5, ERR_ADDR_MODE |
---|
843 | andi. r3,r3,0x0f /* cut off reserved bits */ |
---|
844 | cmpi 0,0,r3,8 |
---|
845 | ble spd_fail |
---|
846 | cmpi 0,0,r3,15 |
---|
847 | bgt spd_fail |
---|
848 | addi r6,r3,-8 /* calculate ADDR_MODE parameter */ |
---|
849 | rlwimi r7,r6,4,24,27 /* set ADDR_MODE field */ |
---|
850 | |
---|
851 | set_dimm_ctrl: |
---|
852 | #ifdef SDC_AUTOPRECH_EN |
---|
853 | oris r7,r7,0x0001 /* set auto precharge EN bit */ |
---|
854 | #endif |
---|
855 | ori r7,r7,1 /* set ENABLE bit */ |
---|
856 | cmpi 0,0,r10,SPD_DIMM0 |
---|
857 | bne 1f |
---|
858 | stw r7,SD_D0_CTRL(r4) |
---|
859 | sync |
---|
860 | b set_dimm_bar |
---|
861 | 1: |
---|
862 | stw r7,SD_D1_CTRL(r4) |
---|
863 | sync |
---|
864 | |
---|
865 | |
---|
866 | /* Program SDRAM DIMMx Base Address Register */ |
---|
867 | |
---|
868 | set_dimm_bar: |
---|
869 | READ_SPD(5) /* get # of Ranks */ |
---|
870 | beq spd_read_fail |
---|
871 | andi. r7,r3,0x7 |
---|
872 | addi r7,r7,1 |
---|
873 | READ_SPD(31) /* Read DIMM rank density */ |
---|
874 | beq spd_read_fail |
---|
875 | rlwinm r5,r3,27,29,31 |
---|
876 | rlwinm r6,r3,3,24,28 |
---|
877 | or r5,r6,r5 /* r5 = Normalized Rank Density byte */ |
---|
878 | lis r8, 0x0080 /* 128MB >> 4 */ |
---|
879 | mullw r8,r8,r5 /* r8 = (rank_size >> 4) */ |
---|
880 | mullw r8,r8,r7 /* r8 = (DIMM_size >> 4) */ |
---|
881 | neg r7,r8 |
---|
882 | rlwinm r7,r7,28,4,31 |
---|
883 | or r7,r7,r11 /* set ADDR field */ |
---|
884 | rlwinm r8,r8,12,20,31 |
---|
885 | add r11,r11,r8 /* set Base Addr for next DIMM */ |
---|
886 | |
---|
887 | cmpi 0,0,r10,SPD_DIMM0 |
---|
888 | bne set_dimm1_size |
---|
889 | stw r7,SD_D0_BAR(r4) |
---|
890 | sync |
---|
891 | li r10,SPD_DIMM1 |
---|
892 | READ_SPD(0) |
---|
893 | bne do_each_dimm |
---|
894 | b spd_done |
---|
895 | |
---|
896 | set_dimm1_size: |
---|
897 | stw r7,SD_D1_BAR(r4) |
---|
898 | sync |
---|
899 | spd_done: |
---|
900 | blr |
---|
901 | |
---|
902 | check_next_slot: |
---|
903 | cmpi 0,0,r10,SPD_DIMM1 |
---|
904 | beq spd_read_fail |
---|
905 | li r10,SPD_DIMM1 |
---|
906 | b do_first_dimm |
---|
907 | spd_read_fail: |
---|
908 | ori r3,r0,0xdead |
---|
909 | b err_hung |
---|
910 | spd_fail: |
---|
911 | li r3,0x0bad |
---|
912 | sync |
---|
913 | err_hung: /* hang here for debugging */ |
---|
914 | nop |
---|
915 | nop |
---|
916 | b err_hung |
---|
917 | |
---|
918 | #endif /* !SDC_HARDCODED_INIT */ |
---|