source: SVN/rincon/u-boot/board/idmr/idmr.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 4.2 KB
Line 
1/*
2 * (C) Copyright 2000-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/immap.h>
26
27int checkboard (void) {
28        puts ("Board: iDMR\n");
29        return 0;
30};
31
32phys_size_t initdram (int board_type) {
33        int i;
34
35        /*
36         * After reset, CS0 is configured to cover entire address space. We
37         * need to configure it to its proper values, so that writes to
38         * CFG_SDRAM_BASE and vicinity during SDRAM controller setup below do
39         * now fall under CS0 (see 16.3.1 of the MCF5271 Reference Manual).
40         */
41
42        /* Flash chipselect, CS0 */
43        /* ;CSAR0: Flash at 0xFF800000 */
44        mbar_writeShort(0x0080, 0xFF80);
45
46        /* CSCR0: Flash 6 waits, 16bit */
47        mbar_writeShort(0x008A, 0x1980);
48
49        /* CSMR0: Flash 8MB, R/W, valid */
50        mbar_writeLong(0x0084, 0x007F0001);
51
52
53        /*
54         * SDRAM configuration proper
55         */
56
57        /*
58         * Address/Data Pin Assignment Reg.: enable address lines 23-21; do
59         * not enable data pins D[15:0], as we have 16 bit port to SDRAM
60         */
61        mbar_writeByte(MCF_GPIO_PAR_AD,
62                        MCF_GPIO_AD_ADDR23 |
63                        MCF_GPIO_AD_ADDR22 |
64                        MCF_GPIO_AD_ADDR21);
65
66        /* No need to configure BS pins - reset values are OK */
67
68        /* Chip Select Pin Assignment Reg.: set CS[1-7] to GPIO */
69        mbar_writeByte(MCF_GPIO_PAR_CS, 0x00);
70
71        /* SDRAM Control Pin Assignment Reg. */
72        mbar_writeByte(MCF_GPIO_PAR_SDRAM,
73                        MCF_GPIO_SDRAM_CSSDCS_00 | /* no matter: PAR_CS=0 */
74                        MCF_GPIO_SDRAM_SDWE |
75                        MCF_GPIO_SDRAM_SCAS |
76                        MCF_GPIO_SDRAM_SRAS |
77                        MCF_GPIO_SDRAM_SCKE |
78                        MCF_GPIO_SDRAM_SDCS_01);
79
80        /*
81         * Wait 100us.  We run the bus at 50Mhz, one cycle is 20ns. So 5
82         * iterations will do, but we do 10 just to be safe.
83         */
84        for (i = 0; i < 10; ++i)
85                asm(" nop");
86
87
88        /* 1. Initialize DRAM Control Register: DCR */
89        mbar_writeShort(MCF_SDRAMC_DCR,
90                        MCF_SDRAMC_DCR_RTIM(0x10) |     /* 65ns */
91                        MCF_SDRAMC_DCR_RC(0x60));       /* 1562 cycles */
92
93
94        /*
95         * 2. Initialize DACR0
96         *
97         * CL: 11 (CL=3: 0x03, 0x02; CL=2: 0x1)
98         * CBM: cmd at A20, bank select bits 21 and up
99         * PS: 16 bit
100         */
101        mbar_writeLong(MCF_SDRAMC_DACR0,
102                        MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18) |
103                        MCF_SDRAMC_DACRn_BA(0x00) |
104                        MCF_SDRAMC_DACRn_CASL(0x03) |
105                        MCF_SDRAMC_DACRn_CBM(0x03) |
106                        MCF_SDRAMC_DACRn_PS(0x03));
107
108        /* Initialize DMR0 */
109        mbar_writeLong(MCF_SDRAMC_DMR0,
110                        MCF_SDRAMC_DMRn_BAM_16M |
111                        MCF_SDRAMC_DMRn_V);
112
113
114        /* 3. Set IP bit in DACR to initiate PALL command */
115        mbar_writeLong(MCF_SDRAMC_DACR0,
116                        mbar_readLong(MCF_SDRAMC_DACR0) |
117                        MCF_SDRAMC_DACRn_IP);
118
119        /* Write to this block to initiate precharge */
120        *(volatile u16 *)(CFG_SDRAM_BASE) = 0xa5a5;
121
122        /*
123         * Wait at least 20ns to allow banks to precharge (t_RP = 20ns). We
124         * wait a wee longer, just to be safe.
125         */
126        for (i = 0; i < 5; ++i)
127                asm(" nop");
128
129
130        /* 4. Set RE bit in DACR */
131        mbar_writeLong(MCF_SDRAMC_DACR0,
132                        mbar_readLong(MCF_SDRAMC_DACR0) |
133                        MCF_SDRAMC_DACRn_RE);
134
135        /*
136         * Wait for at least 8 auto refresh cycles to occur, i.e. at least
137         * 781 bus cycles.
138         */
139        for (i = 0; i < 1000; ++i)
140                asm(" nop");
141
142        /* Finish the configuration by issuing the MRS */
143        mbar_writeLong(MCF_SDRAMC_DACR0,
144                        mbar_readLong(MCF_SDRAMC_DACR0) |
145                        MCF_SDRAMC_DACRn_MRS);
146
147        /*
148         * Write to the SDRAM Mode Register A0-A11 = 0x400
149         *
150         * Write Burst Mode = Programmed Burst Length
151         * Op Mode = Standard Op
152         * CAS Latency = 3
153         * Burst Type = Sequential
154         * Burst Length = 1
155         */
156        *(volatile u32 *)(CFG_SDRAM_BASE + 0x1800) = 0xa5a5a5a5;
157
158        return CFG_SDRAM_SIZE * 1024 * 1024;
159};
160
161
162int testdram (void) {
163
164        /* TODO: XXX XXX XXX */
165        printf ("DRAM test not implemented!\n");
166
167        return (0);
168}
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