source: SVN/rincon/u-boot/board/jse/README.txt @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 1.2 KB
Line 
1JSE Configuration Details
2
3Memory Bank 0 -- Flash chip
4---------------------------
5
60xfff00000 - 0xffffffff
7
8The flash chip is really only 512Kbytes, but the high address bit of
9the 1Meg region is ignored, so the flash is replicated through the
10region. Thus, this is consistent with a flash base address 0xfff80000.
11
12The placement at the end is to be consistent with reset behavior,
13where the processor itself initially uses this bus to load the branch
14vector and start running.
15
16On-Chip Memory
17--------------
18
190xf4000000 - 0xf4000fff
20
21The 405GPr includes a 4K on-chip memory that can be placed however
22software chooses. I choose to place the memory at this address, to
23keep it out of the cachable areas.
24
25
26Memory Bank 1 -- SystemACE Controller
27-------------------------------------
28
290xf0000000 - 0xf00fffff
30
31The SystemACE chip is along on peripheral bank CS#1. We don't need
32much space, but 1Meg is the smallest we can configure the chip to
33allocate. We need it far away from the flash region, because this
34region is set to be non-cached.
35
36
37Internal Peripherals
38--------------------
39
400xef600300 - 0xef6008ff
41
42These are scattered various peripherals internal to the PPC405GPr
43chip.
44
45SDRAM
46-----
47
480x00000000 - 0x07ffffff  (128 MBytes)
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