source: SVN/rincon/u-boot/board/korat/init.S @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 2 years ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 3.0 KB
Line 
1/*
2 *
3 * See file CREDITS for list of people who contributed to this
4 * project.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22#include <ppc_asm.tmpl>
23#include <asm-ppc/mmu.h>
24#include <config.h>
25
26/**************************************************************************
27 * TLB TABLE
28 *
29 * This table is used by the cpu boot code to setup the initial tlb
30 * entries. Rather than make broad assumptions in the cpu source tree,
31 * this table lets each board set things up however they like.
32 *
33 *  Pointer to the table is returned in r1
34 *
35 *************************************************************************/
36    .section .bootpg,"ax"
37    .globl tlbtab
38
39tlbtab:
40        tlbtab_start
41
42        /*
43         * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
44         * speed up boot process. It is patched after relocation to enable SA_I
45         */
46        tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_R|AC_W|AC_X|SA_G )
47
48        /*
49         * TLB entries for SDRAM are not needed on this platform.  They are
50         * generated dynamically in the SPD DDR2 detection routine.
51         */
52
53#ifdef CFG_INIT_RAM_DCACHE
54        /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
55        tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0,
56                  AC_R|AC_W|AC_X|SA_G )
57#endif
58
59        /* TLB-entry for PCI Memory */
60        tlbentry( CFG_PCI_MEMBASE + 0x00000000, SZ_256M,
61                  CFG_PCI_MEMBASE + 0x00000000, 1, AC_R|AC_W|SA_G|SA_I )
62
63        tlbentry( CFG_PCI_MEMBASE + 0x10000000, SZ_256M,
64                  CFG_PCI_MEMBASE + 0x10000000, 1, AC_R|AC_W|SA_G|SA_I )
65
66        tlbentry( CFG_PCI_MEMBASE + 0x20000000, SZ_256M,
67                  CFG_PCI_MEMBASE + 0x20000000, 1, AC_R|AC_W|SA_G|SA_I )
68
69        tlbentry( CFG_PCI_MEMBASE + 0x30000000, SZ_256M,
70                  CFG_PCI_MEMBASE + 0x30000000, 1, AC_R|AC_W|SA_G|SA_I )
71
72        /* TLB-entry for EBC */
73        tlbentry( CFG_CPLD_BASE, SZ_1K, CFG_CPLD_BASE, 1, AC_R|AC_W|SA_G|SA_I )
74
75        /* TLB-entry for Internal Registers & OCM */
76        /* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */
77        tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_R|AC_W|AC_X|SA_I )
78
79        /*TLB-entry PCI registers*/
80        tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|SA_G|SA_I )
81
82        /* TLB-entry for peripherals */
83        tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|SA_G|SA_I)
84
85        /* TLB-entry PCI IO Space - from sr@denx.de */
86        tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|SA_G|SA_I)
87
88        tlbtab_end
89
90#if defined(CONFIG_KORAT_PERMANENT)
91        .globl  korat_branch_absolute
92korat_branch_absolute:
93        mtlr    r3
94        blr
95#endif
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