1 | /* |
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2 | * Memory Setup - initialize memory controller(s) for devices required |
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3 | * to boot and relocate |
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4 | * |
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5 | * See file CREDITS for list of people who contributed to this |
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6 | * project. |
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7 | * |
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8 | * This program is free software; you can redistribute it and/or |
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9 | * modify it under the terms of the GNU General Public License as |
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10 | * published by the Free Software Foundation; either version 2 of |
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11 | * the License, or (at your option) any later version. |
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12 | * |
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13 | * This program is distributed in the hope that it will be useful, |
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14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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16 | * GNU General Public License for more details. |
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17 | * |
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18 | * You should have received a copy of the GNU General Public License |
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19 | * along with this program; if not, write to the Free Software |
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20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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21 | * MA 02111-1307 USA |
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22 | */ |
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23 | |
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24 | |
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25 | #include <config.h> |
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26 | #include <version.h> |
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27 | |
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28 | |
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29 | /* memory controller */ |
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30 | #define BCRX_DEFAULT (0x0000fbe0) |
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31 | #define BCRX_MW_8 (0x00000000) |
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32 | #define BCRX_MW_16 (0x10000000) |
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33 | #define BCRX_MW_32 (0x20000000) |
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34 | #define BCRX_PME (0x08000000) |
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35 | #define BCRX_WP (0x04000000) |
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36 | #define BCRX_WST2_SHIFT (11) |
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37 | #define BCRX_WST1_SHIFT (5) |
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38 | #define BCRX_IDCY_SHIFT (0) |
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39 | |
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40 | /* Bank0 Async Flash */ |
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41 | #define BCR0 (0x80002000) |
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42 | #define BCR0_FLASH (BCRX_MW_32 | (0x08<<BCRX_WST2_SHIFT) | (0x0E<<BCRX_WST1_SHIFT)) |
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43 | |
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44 | /* Bank1 Open */ |
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45 | #define BCR1 (0x80002004) |
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46 | |
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47 | /* Bank2 Not used (EEPROM?) */ |
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48 | #define BCR2 (0x80002008) |
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49 | |
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50 | /* Bank3 Not used */ |
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51 | #define BCR3 (0x8000200C) |
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52 | |
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53 | /* Bank4 PC Card1 */ |
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54 | |
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55 | /* Bank5 PC Card2 */ |
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56 | |
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57 | /* Bank6 CPLD IO Controller Peripherals (slow) */ |
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58 | #define BCR6 (0x80002018) |
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59 | #define BCR6_CPLD_SLOW (BCRX_DEFAULT | BCRX_MW_16) |
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60 | |
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61 | /* Bank7 CPLD IO Controller Peripherals (fast) */ |
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62 | #define BCR7 (0x8000201C) |
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63 | #define BCR7_CPLD_FAST (BCRX_MW_16 | (0x16<<BCRX_WST2_SHIFT) | (0x16<<BCRX_WST1_SHIFT) | (0x2<<BCRX_IDCY_SHIFT)) |
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64 | |
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65 | /* SDRAM */ |
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66 | #define GBLCNFG (0x80002404) |
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67 | #define GC_CKE (0x80000000) |
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68 | #define GC_CKSD (0x40000000) |
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69 | #define GC_LCR (0x00000040) |
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70 | #define GC_SMEMBURST (0x00000020) |
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71 | #define GC_MRS (0x00000002) |
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72 | #define GC_INIT (0x00000001) |
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73 | |
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74 | #define GC_CMD_NORMAL (GC_CKE) |
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75 | #define GC_CMD_MODE (GC_CKE | GC_MRS) |
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76 | #define GC_CMD_SYNCFLASH_LOAD (GC_CKE | GC_MRS | GC_LCR) |
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77 | #define GC_CMD_PRECHARGEALL (GC_CKE | GC_INIT) |
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78 | #define GC_CMD_NOP (GC_CKE | GC_INIT | GC_MRS) |
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79 | |
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80 | #define RFSHTMR (0x80002408) |
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81 | #define RFSHTMR_INIT (10) /* period=100 ns, HCLK=100Mhz, (2048+1-15.6*66) */ |
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82 | #define RFSHTMR_NORMAL (1500) /* period=15.6 us, HCLK=100Mhz, (2048+1-15.6*66) */ |
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83 | |
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84 | #define SDCSCX_BASE (0x80002410) |
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85 | #define SDCSCX_DEFAULT (0x01220008) |
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86 | #define SDCSCX_AUTOPC (0x01000000) |
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87 | #define SDCSCX_RAS2CAS_2 (0x00200000) |
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88 | #define SDCSCX_RAS2CAS_3 (0x00300000) |
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89 | #define SDCSCX_WBL (0x00080000) |
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90 | #define SDCSCX_CASLAT_8 (0x00070000) |
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91 | #define SDCSCX_CASLAT_7 (0x00060000) |
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92 | #define SDCSCX_CASLAT_6 (0x00050000) |
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93 | #define SDCSCX_CASLAT_5 (0x00040000) |
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94 | #define SDCSCX_CASLAT_4 (0x00030000) |
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95 | #define SDCSCX_CASLAT_3 (0x00020000) |
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96 | #define SDCSCX_CASLAT_2 (0x00010000) |
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97 | #define SDCSCX_2KPAGE (0x00000040) |
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98 | #define SDCSCX_SROMLL (0x00000020) |
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99 | #define SDCSCX_SROM512 (0x00000010) |
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100 | #define SDCSCX_4BNK (0x00000008) |
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101 | #define SDCSCX_2BNK (0x00000000) |
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102 | #define SDCSCX_EBW_16 (0x00000004) |
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103 | #define SDCSCX_EBW_32 (0x00000000) |
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104 | |
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105 | #define SDRAM_BASE (0xC0000000) |
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106 | #define SDCSC_BANK_OFFSET (0x10000000) |
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107 | |
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108 | /* |
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109 | * The SDRAM DEVICE MODE PROGRAMMING VALUE |
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110 | */ |
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111 | #define BURST_LENGTH_4 (2 << 10) |
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112 | #define BURST_LENGTH_8 (3 << 10) |
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113 | #define WBURST_LENGTH_BL (0 << 19) |
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114 | #define WBURST_LENGTH_SINGLE (1 << 19) |
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115 | #define CAS_2 (2 << 14) |
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116 | #define CAS_3 (3 << 14) |
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117 | #define BAT_SEQUENTIAL (0 << 13) |
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118 | #define BAT_INTERLEAVED (1 << 13) |
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119 | #define OPM_NORMAL (0 << 17) |
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120 | #define SDRAM_DEVICE_MODE (WBURST_LENGTH_BL|OPM_NORMAL|CAS_3|BAT_SEQUENTIAL|BURST_LENGTH_4) |
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121 | |
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122 | |
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123 | #define TIMER1_BASE (0x80000C00) |
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124 | |
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125 | /* |
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126 | * special lookup flags |
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127 | */ |
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128 | #define DO_MEM_DELAY 1 |
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129 | #define DO_MEM_READ 2 |
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130 | |
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131 | _TEXT_BASE: |
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132 | .word TEXT_BASE |
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133 | |
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134 | .globl lowlevel_init |
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135 | lowlevel_init: |
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136 | mov r9, lr @ save return address |
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137 | |
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138 | /* memory control configuration */ |
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139 | /* make r0 relative the current location so that it */ |
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140 | /* reads INITMEM_DATA out of FLASH rather than memory ! */ |
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141 | /* r0 = current word pointer */ |
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142 | /* r1 = end word location, one word past last actual word */ |
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143 | /* r3 = address for writes, special lookup flags */ |
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144 | /* r4 = value for writes, delay constants, or read addresses */ |
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145 | /* r2 = location for mem reads */ |
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146 | |
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147 | ldr r0, =INITMEM_DATA |
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148 | ldr r1, _TEXT_BASE |
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149 | sub r0, r0, r1 |
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150 | add r1, r0, #112 |
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151 | |
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152 | mem_loop: |
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153 | cmp r1, r0 |
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154 | moveq pc, r9 @ Done |
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155 | |
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156 | ldr r3, [r0], #4 @ Fetch Destination Register Address, or 1 for delay |
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157 | ldr r4, [r0], #4 @ value |
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158 | |
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159 | cmp r3, #DO_MEM_DELAY |
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160 | bleq mem_delay |
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161 | beq mem_loop |
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162 | cmp r3, #DO_MEM_READ |
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163 | ldreq r2, [r4] |
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164 | beq mem_loop |
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165 | str r4, [r3] @ normal register/ram store |
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166 | b mem_loop |
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167 | |
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168 | mem_delay: |
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169 | ldr r5, =TIMER1_BASE |
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170 | mov r6, r4, LSR #1 @ timer resolution is ~2us |
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171 | str r6, [r5] |
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172 | mov r6, #0x88 @ using 508.469KHz clock, enable |
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173 | str r6, [r5, #8] |
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174 | 0: ldr r6, [r5, #4] @ timer value |
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175 | cmp r6, #0 |
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176 | bne 0b |
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177 | mov r6, #0 @ disable timer |
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178 | str r6, [r5, #8] |
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179 | mov pc, lr |
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180 | |
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181 | .ltorg |
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182 | /* the literal pools origin */ |
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183 | |
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184 | INITMEM_DATA: |
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185 | .word BCR0 |
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186 | .word BCR0_FLASH |
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187 | .word BCR6 |
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188 | .word BCR6_CPLD_SLOW |
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189 | .word BCR7 |
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190 | .word BCR7_CPLD_FAST |
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191 | .word SDCSCX_BASE |
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192 | .word (SDCSCX_RAS2CAS_3 | SDCSCX_CASLAT_3 | SDCSCX_SROMLL | SDCSCX_4BNK | SDCSCX_EBW_32) |
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193 | .word GBLCNFG |
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194 | .word GC_CMD_NOP |
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195 | .word DO_MEM_DELAY |
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196 | .word 200 |
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197 | .word GBLCNFG |
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198 | .word GC_CMD_PRECHARGEALL |
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199 | .word RFSHTMR |
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200 | .word RFSHTMR_INIT |
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201 | .word DO_MEM_DELAY |
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202 | .word 8 |
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203 | .word RFSHTMR |
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204 | .word RFSHTMR_NORMAL |
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205 | .word GBLCNFG |
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206 | .word GC_CMD_MODE |
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207 | .word DO_MEM_READ |
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208 | .word (SDRAM_BASE | SDRAM_DEVICE_MODE) |
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209 | .word GBLCNFG |
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210 | .word GC_CMD_NORMAL |
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211 | .word SDCSCX_BASE |
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212 | .word (SDCSCX_AUTOPC | SDCSCX_RAS2CAS_3 | SDCSCX_CASLAT_3 | SDCSCX_SROMLL | SDCSCX_4BNK | SDCSCX_EBW_32) |
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