source: SVN/rincon/u-boot/board/matrix_vision/mvblm7/mvblm7.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 23 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 3.5 KB
Line 
1/*
2 * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
3 *
4 * (C) Copyright 2008
5 * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <ioports.h>
28#include <mpc83xx.h>
29#include <asm/mpc8349_pci.h>
30#include <pci.h>
31#include <spi.h>
32#include <asm/mmu.h>
33#if defined(CONFIG_OF_LIBFDT)
34#include <libfdt.h>
35#endif
36
37#include "mvblm7.h"
38
39int fixed_sdram(void)
40{
41        volatile immap_t *im = (immap_t *)CFG_IMMR;
42        u32 msize = 0;
43        u32 ddr_size;
44        u32 ddr_size_log2;
45
46        msize = CFG_DDR_SIZE;
47        for (ddr_size = msize << 20, ddr_size_log2 = 0;
48             (ddr_size > 1);
49             ddr_size = ddr_size >> 1, ddr_size_log2++) {
50                if (ddr_size & 1)
51                        return -1;
52        }
53        im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
54        im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
55                LAWAR_SIZE);
56
57        im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
58        im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
59        im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
60        im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
61        im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
62        im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
63        im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
64        im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
65        im->ddr.sdram_mode = CFG_DDR_MODE;
66        im->ddr.sdram_interval = CFG_DDR_INTERVAL;
67        im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
68
69        udelay(300);
70
71        im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
72
73        return CFG_DDR_SIZE;
74}
75
76phys_size_t initdram(int board_type)
77{
78        volatile immap_t *im = (immap_t *) CFG_IMMR;
79        u32 msize = 0;
80
81        if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
82                return -1;
83
84        im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
85        msize = fixed_sdram();
86
87        /* return total bus RAM size(bytes) */
88        return msize * 1024 * 1024;
89}
90
91int checkboard(void)
92{
93        puts("Board: Matrix Vision mvBlueLYNX-M7\n");
94
95        return 0;
96}
97
98u8 *dhcp_vendorex_prep(u8 *e)
99{
100        char *ptr;
101
102        /* DHCP vendor-class-identifier = 60 */
103        ptr = getenv("dhcp_vendor-class-identifier");
104        if (ptr) {
105                *e++ = 60;
106                *e++ = strlen(ptr);
107                while (*ptr)
108                        *e++ = *ptr++;
109        }
110        /* DHCP_CLIENT_IDENTIFIER = 61 */
111        ptr = getenv("dhcp_client_id");
112        if (ptr) {
113                *e++ = 61;
114                *e++ = strlen(ptr);
115                while (*ptr)
116                        *e++ = *ptr++;
117        }
118
119        return e;
120}
121
122u8 *dhcp_vendorex_proc(u8 *popt)
123{
124        return NULL;
125}
126
127#ifdef CONFIG_HARD_SPI
128int spi_cs_is_valid(unsigned int bus, unsigned int cs)
129{
130        return bus == 0 && cs == 0;
131}
132
133void spi_cs_activate(struct spi_slave *slave)
134{
135        volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
136
137        iopd->dat &= ~MVBLM7_MMC_CS;
138}
139
140void spi_cs_deactivate(struct spi_slave *slave)
141{
142        volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
143
144        iopd->dat |= ~MVBLM7_MMC_CS;
145}
146#endif
147
148#if defined(CONFIG_OF_BOARD_SETUP)
149void ft_board_setup(void *blob, bd_t *bd)
150{
151        ft_cpu_setup(blob, bd);
152#ifdef CONFIG_PCI
153        ft_pci_setup(blob, bd);
154#endif
155}
156
157#endif
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