1 | /* |
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2 | * (C) Copyright 2000 |
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3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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4 | * Marius Groeger <mgroeger@sysgo.de> |
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5 | * |
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6 | * Board specific routines for the MBX |
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7 | * |
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8 | * - initialisation |
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9 | * - interface to VPD data (mac address, clock speeds) |
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10 | * - memory controller |
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11 | * - serial io initialisation |
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12 | * - ethernet io initialisation |
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13 | * |
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14 | * ----------------------------------------------------------------- |
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15 | * See file CREDITS for list of people who contributed to this |
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16 | * project. |
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17 | * |
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18 | * This program is free software; you can redistribute it and/or |
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19 | * modify it under the terms of the GNU General Public License as |
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20 | * published by the Free Software Foundation; either version 2 of |
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21 | * the License, or (at your option) any later version. |
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22 | * |
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23 | * This program is distributed in the hope that it will be useful, |
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24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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26 | * GNU General Public License for more details. |
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27 | * |
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28 | * You should have received a copy of the GNU General Public License |
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29 | * along with this program; if not, write to the Free Software |
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30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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31 | * MA 02111-1307 USA |
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32 | */ |
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33 | |
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34 | #include <common.h> |
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35 | #include <commproc.h> |
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36 | #include <mpc8xx.h> |
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37 | #include "dimm.h" |
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38 | #include "vpd.h" |
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39 | #include "csr.h" |
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40 | |
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41 | /* ------------------------------------------------------------------------- */ |
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42 | |
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43 | static const uint sdram_table_40[] = { |
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44 | /* DRAM - single read. (offset 0 in upm RAM) |
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45 | */ |
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46 | 0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x30AF0C00, |
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47 | 0xF1BF4805, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
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48 | |
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49 | /* DRAM - burst read. (offset 8 in upm RAM) |
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50 | */ |
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51 | 0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x03AF0C08, |
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52 | 0x0CAF0C04, 0x03AF0C08, 0x0CAF0C04, 0x03AF0C08, |
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53 | 0x0CAF0C04, 0x30AF0C00, 0xF3BF4805, 0xFFFFC005, |
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54 | 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
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55 | |
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56 | /* DRAM - single write. (offset 18 in upm RAM) |
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57 | */ |
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58 | 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x33FF4804, |
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59 | 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
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60 | |
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61 | /* DRAM - burst write. (offset 20 in upm RAM) |
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62 | */ |
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63 | 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C, |
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64 | 0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C, |
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65 | 0x0CFF0C00, 0x33FF4804, 0xFFFFC005, 0xFFFFC005, |
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66 | 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
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67 | |
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68 | /* refresh (offset 30 in upm RAM) |
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69 | */ |
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70 | 0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004, |
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71 | 0x3FFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
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72 | 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
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73 | |
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74 | /* exception. (offset 3c in upm RAM) |
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75 | */ |
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76 | 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, |
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77 | }; |
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78 | |
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79 | static const uint sdram_table_50[] = { |
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80 | /* DRAM - single read. (offset 0 in upm RAM) |
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81 | */ |
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82 | 0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x10AF0C04, |
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83 | 0xF0AF0C00, 0xF3BF4805, 0xFFFFC005, 0xFFFFC005, |
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84 | |
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85 | /* DRAM - burst read. (offset 8 in upm RAM) |
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86 | */ |
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87 | 0xCFAFC004, 0X0FAFC404, 0X0CAF8C04, 0X00AF0C04, |
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88 | /* 0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C04, */ |
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89 | 0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08, |
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90 | 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08, 0X0CAF0C04, |
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91 | /* 0X10AF0C04, 0XF0AFC000, 0XF3FF4805, 0XFFFFC005, */ |
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92 | 0X10AF0C04, 0XF0AFC000, 0XF3BF4805, 0XFFFFC005, |
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93 | |
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94 | /* DRAM - single write. (offset 18 in upm RAM) |
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95 | */ |
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96 | 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x13FF4804, |
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97 | 0xFFFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
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98 | |
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99 | /* DRAM - burst write. (offset 20 in upm RAM) |
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100 | */ |
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101 | 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C, |
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102 | 0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C, |
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103 | 0x0CFF0C00, 0x13FF4804, 0xFFFFC004, 0xFFFFC005, |
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104 | 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
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105 | |
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106 | /* refresh (offset 30 in upm RAM) |
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107 | */ |
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108 | 0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004, |
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109 | 0x1FFFC004, 0xFFFFC004, 0xFFFFC005, 0xFFFFC005, |
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110 | 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
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111 | |
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112 | /* exception. (offset 3c in upm RAM) |
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113 | */ |
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114 | 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, |
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115 | }; |
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116 | |
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117 | /* ------------------------------------------------------------------------- */ |
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118 | |
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119 | static unsigned int get_reffreq(void); |
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120 | static unsigned int board_get_cpufreq(void); |
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121 | |
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122 | void mbx_init (void) |
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123 | { |
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124 | volatile immap_t *immr = (immap_t *) CFG_IMMR; |
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125 | volatile memctl8xx_t *memctl = &immr->im_memctl; |
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126 | ulong speed, refclock, plprcr, sccr; |
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127 | ulong br0_32 = memctl->memc_br0 & 0x400; |
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128 | |
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129 | /* real-time clock status and control register */ |
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130 | immr->im_sitk.sitk_rtcsck = KAPWR_KEY; |
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131 | immr->im_sit.sit_rtcsc = 0x00C3; |
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132 | |
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133 | /* SIEL and SIMASK Registers (see MBX PRG 2-3) */ |
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134 | immr->im_siu_conf.sc_simask = 0x00000000; |
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135 | immr->im_siu_conf.sc_siel = 0xAAAA0000; |
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136 | immr->im_siu_conf.sc_tesr = 0xFFFFFFFF; |
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137 | |
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138 | /* |
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139 | * Prepare access to i2c bus. The MBX offers 3 devices on the i2c bus: |
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140 | * 1. Vital Product Data (contains clock speeds, MAC address etc, see vpd.h) |
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141 | * 2. RAM Specs (see dimm.h) |
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142 | * 2. DIMM Specs (see dimm.h) |
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143 | */ |
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144 | vpd_init (); |
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145 | |
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146 | /* system clock and reset control register */ |
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147 | immr->im_clkrstk.cark_sccrk = KAPWR_KEY; |
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148 | sccr = immr->im_clkrst.car_sccr; |
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149 | sccr &= SCCR_MASK; |
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150 | sccr |= CFG_SCCR; |
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151 | immr->im_clkrst.car_sccr = sccr; |
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152 | |
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153 | speed = board_get_cpufreq (); |
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154 | refclock = get_reffreq (); |
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155 | |
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156 | #if ((CFG_PLPRCR & PLPRCR_MF_MSK) != 0) |
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157 | plprcr = CFG_PLPRCR; |
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158 | #else |
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159 | plprcr = immr->im_clkrst.car_plprcr; |
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160 | plprcr &= PLPRCR_MF_MSK; /* isolate MF field */ |
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161 | plprcr |= CFG_PLPRCR; /* reset control bits */ |
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162 | #endif |
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163 | |
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164 | #ifdef CFG_USE_OSCCLK /* See doc/README.MBX ! */ |
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165 | plprcr |= ((speed + refclock / 2) / refclock - 1) << 20; |
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166 | #endif |
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167 | |
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168 | immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; |
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169 | immr->im_clkrst.car_plprcr = plprcr; |
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170 | |
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171 | /* |
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172 | * preliminary setup of memory controller: |
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173 | * - map Flash, otherwise configuration/status |
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174 | * registers won't be accessible when read |
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175 | * by board_init_f. |
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176 | * - map NVRAM and configuation/status registers. |
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177 | * - map pci registers. |
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178 | * - DON'T map ram yet, this is done in initdram(). |
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179 | */ |
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180 | switch (speed / 1000000) { |
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181 | case 40: |
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182 | memctl->memc_br0 = 0xFE000000 | br0_32 | 1; |
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183 | memctl->memc_or0 = 0xFF800930; |
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184 | memctl->memc_or4 = CFG_NVRAM_OR | 0x920; |
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185 | memctl->memc_br4 = CFG_NVRAM_BASE | 0x401; |
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186 | break; |
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187 | case 50: |
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188 | memctl->memc_br0 = 0xFE000000 | br0_32 | 1; |
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189 | memctl->memc_or0 = 0xFF800940; |
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190 | memctl->memc_or4 = CFG_NVRAM_OR | 0x930; |
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191 | memctl->memc_br4 = CFG_NVRAM_BASE | 0x401; |
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192 | break; |
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193 | default: |
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194 | hang (); |
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195 | break; |
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196 | } |
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197 | #ifdef CONFIG_USE_PCI |
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198 | memctl->memc_or5 = CFG_PCIMEM_OR; |
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199 | memctl->memc_br5 = CFG_PCIMEM_BASE | 0x001; |
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200 | memctl->memc_or6 = CFG_PCIBRIDGE_OR; |
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201 | memctl->memc_br6 = CFG_PCIBRIDGE_BASE | 0x001; |
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202 | #endif |
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203 | /* |
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204 | * FIXME: I do not understand why I have to call this to |
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205 | * initialise the control register here before booting from |
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206 | * the PCMCIA card but if I do not the Linux kernel falls |
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207 | * over in a big heap. If you can answer this question I |
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208 | * would like to know about it. |
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209 | */ |
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210 | board_ether_init(); |
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211 | } |
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212 | |
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213 | void board_serial_init (void) |
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214 | { |
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215 | MBX_CSR1 &= ~(CSR1_COM1EN | CSR1_XCVRDIS); |
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216 | } |
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217 | |
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218 | void board_ether_init (void) |
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219 | { |
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220 | MBX_CSR1 &= ~(CSR1_EAEN | CSR1_ELEN); |
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221 | MBX_CSR1 |= CSR1_ETEN | CSR1_TPEN | CSR1_FDDIS; |
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222 | } |
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223 | |
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224 | static unsigned int board_get_cpufreq (void) |
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225 | { |
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226 | #ifndef CONFIG_8xx_GCLK_FREQ |
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227 | vpd_packet_t *packet; |
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228 | |
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229 | packet = vpd_find_packet (VPD_PID_ICS); |
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230 | return *((ulong *) packet->data); |
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231 | #else |
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232 | return((unsigned int)CONFIG_8xx_GCLK_FREQ ); |
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233 | #endif /* CONFIG_8xx_GCLK_FREQ */ |
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234 | } |
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235 | |
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236 | static unsigned int get_reffreq (void) |
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237 | { |
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238 | vpd_packet_t *packet; |
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239 | |
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240 | packet = vpd_find_packet (VPD_PID_RCS); |
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241 | return *((ulong *) packet->data); |
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242 | } |
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243 | |
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244 | void board_get_enetaddr (uchar * addr) |
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245 | { |
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246 | int i; |
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247 | vpd_packet_t *packet; |
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248 | |
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249 | packet = vpd_find_packet (VPD_PID_EA); |
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250 | for (i = 0; i < 6; i++) |
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251 | addr[i] = packet->data[i]; |
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252 | } |
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253 | |
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254 | /* |
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255 | * Check Board Identity: |
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256 | */ |
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257 | |
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258 | int checkboard (void) |
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259 | { |
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260 | vpd_packet_t *packet; |
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261 | int i; |
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262 | const char *const fmt = |
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263 | "\n *** Warning: Low Battery Status - %s Battery ***"; |
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264 | |
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265 | puts ("Board: "); |
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266 | |
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267 | packet = vpd_find_packet (VPD_PID_PID); |
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268 | for (i = 0; i < packet->size; i++) { |
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269 | serial_putc (packet->data[i]); |
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270 | } |
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271 | packet = vpd_find_packet (VPD_PID_MT); |
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272 | for (i = 0; i < packet->size; i++) { |
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273 | serial_putc (packet->data[i]); |
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274 | } |
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275 | serial_putc ('('); |
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276 | packet = vpd_find_packet (VPD_PID_FAN); |
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277 | for (i = 0; i < packet->size; i++) { |
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278 | serial_putc (packet->data[i]); |
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279 | } |
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280 | serial_putc (')'); |
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281 | |
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282 | if (!(MBX_CSR2 & SR2_BATGD)) |
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283 | printf (fmt, "On-Board"); |
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284 | if (!(MBX_CSR2 & SR2_NVBATGD)) |
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285 | printf (fmt, "NVRAM"); |
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286 | |
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287 | serial_putc ('\n'); |
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288 | |
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289 | return (0); |
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290 | } |
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291 | |
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292 | /* ------------------------------------------------------------------------- */ |
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293 | |
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294 | static ulong get_ramsize (dimm_t * dimm) |
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295 | { |
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296 | ulong size = 0; |
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297 | |
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298 | if (dimm->fmt == 1 || dimm->fmt == 2 || dimm->fmt == 3 |
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299 | || dimm->fmt == 4) { |
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300 | size = (1 << (dimm->n_row + dimm->n_col)) * dimm->n_banks * |
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301 | ((dimm->data_w_hi << 8 | dimm->data_w_lo) / 8); |
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302 | } |
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303 | |
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304 | return size; |
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305 | } |
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306 | |
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307 | phys_size_t initdram (int board_type) |
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308 | { |
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309 | volatile immap_t *immap = (immap_t *) CFG_IMMR; |
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310 | volatile memctl8xx_t *memctl = &immap->im_memctl; |
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311 | unsigned long ram_sz = 0; |
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312 | unsigned long dimm_sz = 0; |
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313 | dimm_t vpd_dimm, vpd_dram; |
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314 | unsigned int speed = board_get_cpufreq () / 1000000; |
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315 | |
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316 | if (vpd_read (0xa2, (uchar *) & vpd_dimm, sizeof (vpd_dimm), 0) > 0) { |
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317 | dimm_sz = get_ramsize (&vpd_dimm); |
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318 | } |
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319 | if (vpd_read (0xa6, (uchar *) & vpd_dram, sizeof (vpd_dram), 0) > 0) { |
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320 | ram_sz = get_ramsize (&vpd_dram); |
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321 | } |
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322 | |
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323 | /* |
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324 | * Only initialize memory controller when running from FLASH. |
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325 | * When running from RAM, don't touch it. |
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326 | */ |
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327 | if ((ulong) initdram & 0xff000000) { |
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328 | ulong dimm_bank; |
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329 | ulong br0_32 = memctl->memc_br0 & 0x400; |
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330 | |
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331 | switch (speed) { |
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332 | case 40: |
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333 | upmconfig (UPMA, (uint *) sdram_table_40, |
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334 | sizeof (sdram_table_40) / sizeof (uint)); |
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335 | memctl->memc_mptpr = 0x0200; |
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336 | memctl->memc_mamr = dimm_sz ? 0x06801000 : 0x13801000; |
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337 | memctl->memc_or7 = 0xff800930; |
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338 | memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1; |
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339 | break; |
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340 | case 50: |
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341 | upmconfig (UPMA, (uint *) sdram_table_50, |
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342 | sizeof (sdram_table_50) / sizeof (uint)); |
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343 | memctl->memc_mptpr = 0x0200; |
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344 | memctl->memc_mamr = dimm_sz ? 0x08801000 : 0x1880100; |
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345 | memctl->memc_or7 = 0xff800940; |
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346 | memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1; |
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347 | break; |
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348 | default: |
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349 | hang (); |
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350 | break; |
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351 | } |
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352 | |
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353 | /* now map ram and dimm, largest one first */ |
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354 | dimm_bank = dimm_sz / 2; |
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355 | if (!dimm_sz) { |
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356 | memctl->memc_or1 = ~(ram_sz - 1) | 0x400; |
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357 | memctl->memc_br1 = CFG_SDRAM_BASE | 0x81; |
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358 | memctl->memc_br2 = 0; |
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359 | memctl->memc_br3 = 0; |
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360 | } else if (ram_sz > dimm_bank) { |
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361 | memctl->memc_or1 = ~(ram_sz - 1) | 0x400; |
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362 | memctl->memc_br1 = CFG_SDRAM_BASE | 0x81; |
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363 | memctl->memc_or2 = ~(dimm_bank - 1) | 0x400; |
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364 | memctl->memc_br2 = (CFG_SDRAM_BASE + ram_sz) | 0x81; |
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365 | memctl->memc_or3 = ~(dimm_bank - 1) | 0x400; |
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366 | memctl->memc_br3 = (CFG_SDRAM_BASE + ram_sz + dimm_bank) \ |
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367 | | 0x81; |
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368 | } else { |
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369 | memctl->memc_or2 = ~(dimm_bank - 1) | 0x400; |
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370 | memctl->memc_br2 = CFG_SDRAM_BASE | 0x81; |
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371 | memctl->memc_or3 = ~(dimm_bank - 1) | 0x400; |
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372 | memctl->memc_br3 = (CFG_SDRAM_BASE + dimm_bank) | 0x81; |
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373 | memctl->memc_or1 = ~(ram_sz - 1) | 0x400; |
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374 | memctl->memc_br1 = (CFG_SDRAM_BASE + dimm_sz) | 0x81; |
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375 | } |
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376 | } |
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377 | |
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378 | return ram_sz + dimm_sz; |
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379 | } |
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