1 | /* |
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2 | * (C) Copyright 2001 |
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3 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
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4 | * |
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5 | * (C) Copyright 2001 |
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6 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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7 | * |
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8 | * Modified for the MP2USB by (C) Copyright 2005 Eric Benard |
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9 | * ebenard@eukrea.com |
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10 | * |
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11 | * See file CREDITS for list of people who contributed to this |
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12 | * project. |
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13 | * |
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14 | * This program is free software; you can redistribute it and/or |
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15 | * modify it under the terms of the GNU General Public License as |
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16 | * published by the Free Software Foundation; either version 2 of |
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17 | * the License, or (at your option) any later version. |
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18 | * |
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19 | * This program is distributed in the hope that it will be useful, |
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20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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22 | * GNU General Public License for more details. |
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23 | * |
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24 | * You should have received a copy of the GNU General Public License |
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25 | * along with this program; if not, write to the Free Software |
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26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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27 | * MA 02111-1307 USA |
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28 | */ |
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29 | |
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30 | #include <common.h> |
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31 | #include <linux/byteorder/swab.h> |
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32 | |
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33 | #define CFG_MAX_FLASH_BANKS 1 |
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34 | #define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */ |
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35 | |
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36 | flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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37 | |
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38 | #define FLASH_PORT_WIDTH ushort |
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39 | #define FLASH_PORT_WIDTHV vu_short |
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40 | #define SWAP(x) __swab16(x) |
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41 | |
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42 | #define FPW FLASH_PORT_WIDTH |
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43 | #define FPWV FLASH_PORT_WIDTHV |
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44 | |
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45 | #define mb() __asm__ __volatile__ ("" : : : "memory") |
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46 | |
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47 | /* Intel-compatible flash commands */ |
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48 | #define INTEL_PROGRAM 0x00100010 |
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49 | #define INTEL_ERASE 0x00200020 |
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50 | #define INTEL_PROG 0x00400040 |
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51 | #define INTEL_CLEAR 0x00500050 |
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52 | #define INTEL_LOCKBIT 0x00600060 |
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53 | #define INTEL_PROTECT 0x00010001 |
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54 | #define INTEL_STATUS 0x00700070 |
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55 | #define INTEL_READID 0x00900090 |
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56 | #define INTEL_SUSPEND 0x00B000B0 |
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57 | #define INTEL_CONFIRM 0x00D000D0 |
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58 | #define INTEL_RESET 0xFFFFFFFF |
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59 | |
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60 | /* Intel-compatible flash status bits */ |
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61 | #define INTEL_FINISHED 0x00800080 |
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62 | #define INTEL_OK 0x00800080 |
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63 | |
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64 | /*----------------------------------------------------------------------- |
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65 | * Functions |
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66 | */ |
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67 | static ulong flash_get_size (FPW *addr, flash_info_t *info); |
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68 | static int write_data (flash_info_t *info, ulong dest, FPW data); |
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69 | static void flash_get_offsets (ulong base, flash_info_t *info); |
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70 | void inline spin_wheel (void); |
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71 | |
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72 | /*----------------------------------------------------------------------- |
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73 | */ |
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74 | |
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75 | unsigned long flash_init (void) |
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76 | { |
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77 | int i; |
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78 | ulong size = 0; |
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79 | |
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80 | for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { |
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81 | switch (i) { |
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82 | case 0: |
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83 | flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); |
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84 | flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); |
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85 | break; |
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86 | default: |
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87 | panic ("configured too many flash banks!\n"); |
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88 | break; |
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89 | } |
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90 | size += flash_info[i].size; |
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91 | } |
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92 | |
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93 | /* Protect monitor and environment sectors |
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94 | */ |
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95 | flash_protect ( FLAG_PROTECT_SET, |
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96 | CFG_FLASH_BASE, |
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97 | CFG_FLASH_BASE + monitor_flash_len - 1, |
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98 | &flash_info[0] ); |
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99 | |
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100 | flash_protect ( FLAG_PROTECT_SET, |
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101 | CONFIG_ENV_ADDR, |
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102 | CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] ); |
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103 | |
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104 | return size; |
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105 | } |
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106 | |
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107 | /*----------------------------------------------------------------------- |
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108 | */ |
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109 | static void flash_get_offsets (ulong base, flash_info_t *info) |
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110 | { |
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111 | int i; |
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112 | |
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113 | if (info->flash_id == FLASH_UNKNOWN) { |
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114 | return; |
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115 | } |
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116 | |
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117 | if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { |
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118 | for (i = 0; i < info->sector_count; i++) { |
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119 | info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); |
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120 | info->protect[i] = 0; |
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121 | } |
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122 | } |
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123 | } |
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124 | |
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125 | /*----------------------------------------------------------------------- |
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126 | */ |
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127 | void flash_print_info (flash_info_t *info) |
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128 | { |
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129 | int i; |
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130 | |
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131 | if (info->flash_id == FLASH_UNKNOWN) { |
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132 | printf ("missing or unknown FLASH type\n"); |
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133 | return; |
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134 | } |
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135 | |
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136 | switch (info->flash_id & FLASH_VENDMASK) { |
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137 | case FLASH_MAN_INTEL: |
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138 | printf ("INTEL "); |
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139 | break; |
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140 | default: |
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141 | printf ("Unknown Vendor "); |
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142 | break; |
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143 | } |
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144 | |
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145 | switch (info->flash_id & FLASH_TYPEMASK) { |
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146 | case FLASH_28F640J3A: |
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147 | printf ("28F640J3A\n"); |
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148 | break; |
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149 | case FLASH_28F128J3A: |
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150 | printf ("28F128J3A\n"); |
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151 | break; |
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152 | default: |
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153 | printf ("Unknown Chip Type\n"); |
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154 | break; |
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155 | } |
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156 | |
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157 | printf (" Size: %ld MB in %d Sectors\n", |
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158 | info->size >> 20, info->sector_count); |
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159 | |
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160 | printf (" Sector Start Addresses:"); |
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161 | for (i = 0; i < info->sector_count; ++i) { |
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162 | if ((i % 5) == 0) |
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163 | printf ("\n "); |
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164 | printf (" %08lX%s", |
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165 | info->start[i], |
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166 | info->protect[i] ? " (RO)" : " "); |
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167 | } |
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168 | printf ("\n"); |
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169 | return; |
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170 | } |
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171 | |
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172 | /* |
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173 | * The following code cannot be run from FLASH! |
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174 | */ |
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175 | static ulong flash_get_size (FPW *addr, flash_info_t *info) |
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176 | { |
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177 | volatile FPW value; |
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178 | |
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179 | /* Write auto select command: read Manufacturer ID */ |
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180 | addr[0x5555] = (FPW) 0x00AA00AA; |
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181 | addr[0x2AAA] = (FPW) 0x00550055; |
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182 | addr[0x5555] = (FPW) 0x00900090; |
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183 | |
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184 | mb (); |
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185 | value = addr[0]; |
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186 | |
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187 | switch (value) { |
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188 | |
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189 | case (FPW) INTEL_MANUFACT: |
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190 | info->flash_id = FLASH_MAN_INTEL; |
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191 | break; |
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192 | |
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193 | default: |
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194 | info->flash_id = FLASH_UNKNOWN; |
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195 | info->sector_count = 0; |
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196 | info->size = 0; |
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197 | addr[0] = (FPW) INTEL_RESET; /* restore read mode */ |
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198 | return (0); /* no or unknown flash */ |
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199 | } |
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200 | |
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201 | mb (); |
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202 | value = addr[1]; /* device ID */ |
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203 | |
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204 | switch (value) { |
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205 | |
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206 | case (FPW) INTEL_ID_28F640J3A: |
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207 | info->flash_id += FLASH_28F640J3A; |
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208 | info->sector_count = 64; |
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209 | info->size = 0x00800000; |
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210 | break; /* => 8 MB */ |
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211 | |
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212 | case (FPW) INTEL_ID_28F128J3A: |
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213 | info->flash_id += FLASH_28F128J3A; |
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214 | info->sector_count = 128; |
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215 | info->size = 0x01000000; |
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216 | break; /* => 16 MB */ |
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217 | |
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218 | default: |
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219 | info->flash_id = FLASH_UNKNOWN; |
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220 | break; |
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221 | } |
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222 | |
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223 | if (info->sector_count > CFG_MAX_FLASH_SECT) { |
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224 | printf ("** ERROR: sector count %d > max (%d) **\n", |
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225 | info->sector_count, CFG_MAX_FLASH_SECT); |
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226 | info->sector_count = CFG_MAX_FLASH_SECT; |
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227 | } |
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228 | |
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229 | addr[0] = (FPW) INTEL_RESET; /* restore read mode */ |
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230 | |
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231 | return (info->size); |
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232 | } |
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233 | |
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234 | |
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235 | /*----------------------------------------------------------------------- |
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236 | */ |
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237 | |
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238 | int flash_erase (flash_info_t *info, int s_first, int s_last) |
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239 | { |
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240 | int prot, sect; |
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241 | ulong type, start, last; |
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242 | int rcode = 0; |
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243 | int cflag, iflag; |
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244 | |
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245 | if ((s_first < 0) || (s_first > s_last)) { |
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246 | if (info->flash_id == FLASH_UNKNOWN) { |
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247 | printf ("- missing\n"); |
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248 | } else { |
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249 | printf ("- no sectors to erase\n"); |
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250 | } |
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251 | return 1; |
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252 | } |
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253 | |
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254 | type = (info->flash_id & FLASH_VENDMASK); |
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255 | if ((type != FLASH_MAN_INTEL)) { |
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256 | printf ("Can't erase unknown flash type %08lx - aborted\n", |
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257 | info->flash_id); |
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258 | return 1; |
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259 | } |
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260 | |
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261 | prot = 0; |
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262 | for (sect = s_first; sect <= s_last; ++sect) { |
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263 | if (info->protect[sect]) { |
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264 | prot++; |
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265 | } |
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266 | } |
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267 | |
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268 | if (prot) { |
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269 | printf ("- Warning: %d protected sectors will not be erased!\n", |
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270 | prot); |
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271 | } else { |
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272 | printf ("\n"); |
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273 | } |
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274 | |
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275 | start = get_timer (0); |
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276 | last = start; |
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277 | |
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278 | /* |
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279 | * Disable interrupts which might cause a timeout |
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280 | * here. Remember that our exception vectors are |
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281 | * at address 0 in the flash, and we don't want a |
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282 | * (ticker) exception to happen while the flash |
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283 | * chip is in programming mode. |
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284 | */ |
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285 | cflag = icache_status (); |
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286 | icache_disable (); |
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287 | /* Disable interrupts which might cause a timeout here */ |
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288 | iflag = disable_interrupts (); |
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289 | |
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290 | /* Start erase on unprotected sectors */ |
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291 | for (sect = s_first; sect <= s_last; sect++) { |
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292 | if (info->protect[sect] == 0) { /* not protected */ |
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293 | FPWV *addr = (FPWV *) (info->start[sect]); |
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294 | FPW status; |
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295 | |
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296 | printf ("Erasing sector %2d ... ", sect); |
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297 | |
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298 | /* arm simple, non interrupt dependent timer */ |
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299 | reset_timer_masked (); |
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300 | |
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301 | *addr = (FPW) INTEL_CLEAR; /* clear status register */ |
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302 | *addr = (FPW) INTEL_ERASE; /* erase setup */ |
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303 | *addr = (FPW) INTEL_CONFIRM; /* erase confirm */ |
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304 | |
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305 | while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { |
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306 | if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { |
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307 | printf ("Timeout\n"); |
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308 | *addr = (FPW) INTEL_SUSPEND; /* suspend erase */ |
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309 | *addr = (FPW) INTEL_RESET; /* reset to read mode */ |
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310 | rcode = 1; |
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311 | break; |
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312 | } |
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313 | } |
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314 | |
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315 | *addr = (FPWV)INTEL_CLEAR; /* clear status register cmd. */ |
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316 | *addr = (FPWV)INTEL_RESET; /* resest to read mode */ |
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317 | |
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318 | printf (" done\n"); |
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319 | } |
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320 | } |
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321 | |
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322 | if (iflag) |
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323 | enable_interrupts (); |
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324 | |
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325 | if (cflag) |
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326 | icache_enable (); |
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327 | |
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328 | return rcode; |
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329 | } |
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330 | |
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331 | /*----------------------------------------------------------------------- |
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332 | * Copy memory to flash, returns: |
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333 | * 0 - OK |
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334 | * 1 - write timeout |
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335 | * 2 - Flash not erased |
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336 | * 4 - Flash not identified |
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337 | */ |
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338 | |
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339 | int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
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340 | { |
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341 | ulong cp, wp; |
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342 | FPW data; |
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343 | int count, i, l, rc, port_width; |
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344 | |
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345 | if (info->flash_id == FLASH_UNKNOWN) { |
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346 | return 4; |
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347 | } |
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348 | |
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349 | /* get lower word aligned address */ |
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350 | wp = (addr & ~1); |
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351 | port_width = 2; |
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352 | |
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353 | /* |
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354 | * handle unaligned start bytes |
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355 | */ |
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356 | if ((l = addr - wp) != 0) { |
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357 | data = 0; |
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358 | for (i = 0, cp = wp; i < l; ++i, ++cp) { |
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359 | data = (data << 8) | (*(uchar *) cp); |
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360 | } |
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361 | for (; i < port_width && cnt > 0; ++i) { |
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362 | data = (data << 8) | *src++; |
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363 | --cnt; |
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364 | ++cp; |
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365 | } |
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366 | for (; cnt == 0 && i < port_width; ++i, ++cp) { |
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367 | data = (data << 8) | (*(uchar *) cp); |
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368 | } |
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369 | |
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370 | if ((rc = write_data (info, wp, SWAP (data))) != 0) { |
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371 | return (rc); |
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372 | } |
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373 | wp += port_width; |
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374 | } |
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375 | |
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376 | /* |
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377 | * handle word aligned part |
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378 | */ |
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379 | count = 0; |
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380 | while (cnt >= port_width) { |
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381 | data = 0; |
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382 | for (i = 0; i < port_width; ++i) { |
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383 | data = (data << 8) | *src++; |
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384 | } |
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385 | if ((rc = write_data (info, wp, SWAP (data))) != 0) { |
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386 | return (rc); |
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387 | } |
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388 | wp += port_width; |
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389 | cnt -= port_width; |
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390 | if (count++ > 0x800) { |
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391 | spin_wheel (); |
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392 | count = 0; |
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393 | } |
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394 | } |
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395 | |
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396 | if (cnt == 0) { |
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397 | return (0); |
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398 | } |
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399 | |
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400 | /* |
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401 | * handle unaligned tail bytes |
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402 | */ |
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403 | data = 0; |
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404 | for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { |
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405 | data = (data << 8) | *src++; |
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406 | --cnt; |
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407 | } |
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408 | for (; i < port_width; ++i, ++cp) { |
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409 | data = (data << 8) | (*(uchar *) cp); |
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410 | } |
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411 | |
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412 | return (write_data (info, wp, SWAP (data))); |
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413 | } |
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414 | |
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415 | /*----------------------------------------------------------------------- |
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416 | * Write a word or halfword to Flash, returns: |
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417 | * 0 - OK |
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418 | * 1 - write timeout |
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419 | * 2 - Flash not erased |
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420 | */ |
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421 | static int write_data (flash_info_t *info, ulong dest, FPW data) |
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422 | { |
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423 | FPWV *addr = (FPWV *) dest; |
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424 | ulong status; |
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425 | int cflag, iflag; |
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426 | |
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427 | /* Check if Flash is (sufficiently) erased */ |
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428 | if ((*addr & data) != data) { |
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429 | printf ("not erased at %08lx (%lx)\n", (ulong) addr, (ulong) *addr); |
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430 | return (2); |
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431 | } |
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432 | /* |
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433 | * Disable interrupts which might cause a timeout |
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434 | * here. Remember that our exception vectors are |
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435 | * at address 0 in the flash, and we don't want a |
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436 | * (ticker) exception to happen while the flash |
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437 | * chip is in programming mode. |
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438 | */ |
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439 | cflag = icache_status (); |
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440 | icache_disable (); |
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441 | /* Disable interrupts which might cause a timeout here */ |
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442 | iflag = disable_interrupts (); |
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443 | |
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444 | *addr = (FPW) INTEL_PROG; /* write setup */ |
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445 | *addr = data; |
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446 | |
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447 | /* arm simple, non interrupt dependent timer */ |
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448 | reset_timer_masked (); |
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449 | |
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450 | /* wait while polling the status register */ |
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451 | while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { |
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452 | if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { |
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453 | *addr = (FPW) INTEL_RESET; /* restore read mode */ |
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454 | return (1); |
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455 | } |
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456 | } |
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457 | |
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458 | *addr = (FPW) INTEL_RESET; /* restore read mode */ |
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459 | |
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460 | if (iflag) |
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461 | enable_interrupts (); |
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462 | |
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463 | if (cflag) |
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464 | icache_enable (); |
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465 | |
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466 | return (0); |
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467 | } |
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468 | |
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469 | void inline spin_wheel (void) |
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470 | { |
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471 | static int p = 0; |
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472 | static char w[] = "\\/-"; |
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473 | |
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474 | printf ("\010%c", w[p]); |
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475 | (++p == 3) ? (p = 0) : 0; |
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476 | } |
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477 | |
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478 | /*----------------------------------------------------------------------- |
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479 | * Set/Clear sector's lock bit, returns: |
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480 | * 0 - OK |
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481 | * 1 - Error (timeout, voltage problems, etc.) |
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482 | */ |
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483 | int flash_real_protect(flash_info_t *info, long sector, int prot) |
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484 | { |
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485 | int i; |
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486 | int rc = 0; |
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487 | FPWV *addr = (FPWV *)(info->start[sector]); |
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488 | int flag = disable_interrupts(); |
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489 | |
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490 | *addr = (FPW) INTEL_CLEAR; /* Clear status register */ |
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491 | if (prot) { /* Set sector lock bit */ |
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492 | *addr = (FPW) INTEL_LOCKBIT; /* Sector lock bit */ |
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493 | *addr = (FPW) INTEL_PROTECT; /* set */ |
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494 | } |
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495 | else { /* Clear sector lock bit */ |
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496 | *addr = (FPW) INTEL_LOCKBIT; /* All sectors lock bits */ |
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497 | *addr = (FPW) INTEL_CONFIRM; /* clear */ |
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498 | } |
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499 | |
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500 | reset_timer_masked (); |
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501 | |
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502 | while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { |
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503 | if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT) { |
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504 | printf("Flash lock bit operation timed out\n"); |
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505 | rc = 1; |
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506 | break; |
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507 | } |
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508 | } |
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509 | |
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510 | if (*addr != (FPW) INTEL_OK) { |
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511 | printf("Flash lock bit operation failed at %08X, CSR=%08X\n", |
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512 | (uint)addr, (uint)*addr); |
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513 | rc = 1; |
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514 | } |
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515 | |
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516 | if (!rc) |
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517 | info->protect[sector] = prot; |
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518 | |
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519 | /* |
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520 | * Clear lock bit command clears all sectors lock bits, so |
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521 | * we have to restore lock bits of protected sectors. |
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522 | */ |
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523 | if (!prot) |
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524 | { |
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525 | for (i = 0; i < info->sector_count; i++) |
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526 | { |
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527 | if (info->protect[i]) |
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528 | { |
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529 | reset_timer_masked (); |
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530 | addr = (FPWV *) (info->start[i]); |
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531 | *addr = (FPW) INTEL_LOCKBIT; /* Sector lock bit */ |
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532 | *addr = (FPW) INTEL_PROTECT; /* set */ |
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533 | while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) |
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534 | { |
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535 | if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT) |
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536 | { |
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537 | printf("Flash lock bit operation timed out\n"); |
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538 | rc = 1; |
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539 | break; |
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540 | } |
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541 | } |
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542 | } |
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543 | } |
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544 | } |
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545 | |
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546 | if (flag) |
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547 | enable_interrupts(); |
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548 | |
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549 | *addr = (FPW) INTEL_RESET; /* Reset to read array mode */ |
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550 | |
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551 | return rc; |
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552 | } |
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