source: SVN/rincon/u-boot/board/mpl/mip405/init.S @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 6.9 KB
Line 
1/*------------------------------------------------------------------------------+
2 *
3 *      This source code has been made available to you by IBM on an AS-IS
4 *      basis.  Anyone receiving this source is licensed under IBM
5 *      copyrights to use it in any way he or she deems fit, including
6 *      copying it, modifying it, compiling it, and redistributing it either
7 *      with or without modifications.  No license under IBM patents or
8 *      patent applications is to be implied by the copyright license.
9 *
10 *      Any user of this software should understand that IBM cannot provide
11 *      technical support for this software and will not be responsible for
12 *      any consequences resulting from the use of this software.
13 *
14 *      Any person who transfers this source code or any derivative work
15 *      must include the IBM copyright notice, this paragraph, and the
16 *      preceding two paragraphs in the transferred software.
17 *
18 *      COPYRIGHT   I B M   CORPORATION 1995
19 *      LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
20 *-------------------------------------------------------------------------------*/
21
22/*-----------------------------------------------------------------------------
23 * Function:     ext_bus_cntlr_init
24 * Description:  Initializes the External Bus Controller for the external
25 *              peripherals. IMPORTANT: For pass1 this code must run from
26 *              cache since you can not reliably change a peripheral banks
27 *              timing register (pbxap) while running code from that bank.
28 *              For ex., since we are running from ROM on bank 0, we can NOT
29 *              execute the code that modifies bank 0 timings from ROM, so
30 *              we run it from cache.
31 *      Bank 0 - Flash or Multi Purpose Socket
32 *      Bank 1 - Multi Purpose Socket or Flash (set in C-Code)
33 *      Bank 2 - UART 1 (set in C-Code)
34 *      Bank 3 - UART 2 (set in C-Code)
35 *      Bank 4 - not used
36 *      Bank 5 - not used
37 *      Bank 6 - not used
38 *      Bank 7 - PLD Register
39 *-----------------------------------------------------------------------------*/
40#include <ppc4xx.h>
41
42#define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
43
44#include <configs/MIP405.h>
45#include <ppc_asm.tmpl>
46#include <ppc_defs.h>
47
48#include <asm/cache.h>
49#include <asm/mmu.h>
50#include "mip405.h"
51
52
53  .globl ext_bus_cntlr_init
54ext_bus_cntlr_init:
55  mflr   r4                      /* save link register */
56  mfdcr  r3,strap                /* get strapping reg */
57  andi.  r0, r3, PSR_ROM_LOC     /* mask out irrelevant bits */
58  bnelr                          /* jump back if PCI boot */
59
60  bl      ..getAddr
61..getAddr:
62  mflr    r3                      /* get address of ..getAddr */
63  mtlr    r4                      /* restore link register */
64  addi    r4,0,14                 /* set ctr to 14; used to prefetch */
65  mtctr   r4                      /* 14 cache lines to fit this function */
66                                   /* in cache (gives us 8x14=112 instrctns) */
67..ebcloop:
68  icbt    r0,r3                   /* prefetch cache line for addr in r3 */
69  addi    r3,r3,32                                                              /* move to next cache line */
70  bdnz    ..ebcloop               /* continue for 14 cache lines */
71
72   /*-------------------------------------------------------------------
73    * Delay to ensure all accesses to ROM are complete before changing
74    * bank 0 timings.
75    *------------------------------------------------------------------- */
76        addis   r3,0,0x0
77  ori     r3,r3,0xA000
78  mtctr   r3
79..spinlp:
80  bdnz    ..spinlp                /* spin loop */
81
82        /*-----------------------------------------------------------------------
83         * decide boot up mode
84         *----------------------------------------------------------------------- */
85        addi            r4,0,pb0cr
86        mtdcr           ebccfga,r4
87        mfdcr           r4,ebccfgd
88
89        andi.           r0, r4, 0x2000                  /* mask out irrelevant bits */
90        beq             0f                              /* jump if 8 bit bus width */
91
92        /* setup 16 bit things
93   *-----------------------------------------------------------------------
94   * Memory Bank 0 (16 Bit Flash) initialization
95   *---------------------------------------------------------------------- */
96
97        addi    r4,0,pb0ap
98        mtdcr   ebccfga,r4
99        addis   r4,0,(FLASH_AP_B)@h
100        ori     r4,r4,(FLASH_AP_B)@l
101        mtdcr   ebccfgd,r4
102
103        addi    r4,0,pb0cr
104        mtdcr   ebccfga,r4
105        /* BS=0x010(4MB),BU=0x3(R/W), */
106        addis   r4,0,(FLASH_CR_B)@h
107        ori     r4,r4,(FLASH_CR_B)@l
108        mtdcr   ebccfgd,r4
109        b                               1f
110
1110:
112
113        /* 8Bit boot mode: */
114        /*-----------------------------------------------------------------------
115        * Memory Bank 0 Multi Purpose Socket initialization
116        *----------------------------------------------------------------------- */
117        /* 0x7F8FFE80 slowest boot */
118        addi    r4,0,pb0ap
119        mtdcr   ebccfga,r4
120        addis   r4,0,(MPS_AP_B)@h
121        ori     r4,r4,(MPS_AP_B)@l
122        mtdcr   ebccfgd,r4
123
124        addi    r4,0,pb0cr
125        mtdcr   ebccfga,r4
126        /* BS=0x010(4MB),BU=0x3(R/W), */
127        addis   r4,0,(MPS_CR_B)@h
128        ori     r4,r4,(MPS_CR_B)@l
129
130        mtdcr   ebccfgd,r4
131
132
1331:
134  /*-----------------------------------------------------------------------
135   * Memory Bank 2-3-4-5-6 (not used) initialization
136   *-----------------------------------------------------------------------*/
137  addi    r4,0,pb1cr
138  mtdcr   ebccfga,r4
139  addis   r4,0,0x0000
140  ori     r4,r4,0x0000
141  mtdcr   ebccfgd,r4
142
143  addi    r4,0,pb2cr
144  mtdcr   ebccfga,r4
145  addis   r4,0,0x0000
146  ori     r4,r4,0x0000
147  mtdcr   ebccfgd,r4
148
149  addi    r4,0,pb3cr
150  mtdcr   ebccfga,r4
151  addis   r4,0,0x0000
152  ori     r4,r4,0x0000
153  mtdcr   ebccfgd,r4
154
155  addi    r4,0,pb4cr
156  mtdcr   ebccfga,r4
157  addis   r4,0,0x0000
158  ori     r4,r4,0x0000
159  mtdcr   ebccfgd,r4
160
161  addi    r4,0,pb5cr
162  mtdcr   ebccfga,r4
163  addis   r4,0,0x0000
164  ori     r4,r4,0x0000
165  mtdcr   ebccfgd,r4
166
167  addi    r4,0,pb6cr
168  mtdcr   ebccfga,r4
169  addis   r4,0,0x0000
170  ori     r4,r4,0x0000
171  mtdcr   ebccfgd,r4
172
173  addi    r4,0,pb7cr
174  mtdcr   ebccfga,r4
175  addis   r4,0,0x0000
176  ori     r4,r4,0x0000
177  mtdcr   ebccfgd,r4
178  nop                           /* pass2 DCR errata #8 */
179  blr
180
181#if defined(CONFIG_BOOT_PCI)
182    .section .bootpg,"ax"
183    .globl _start_pci
184/*******************************************
185 */
186
187_start_pci:
188  /* first handle errata #68 / PCI_18 */
189  iccci   r0, r0          /* invalidate I-cache */
190  lis     r31, 0
191  mticcr  r31             /* ICCR = 0 (all uncachable) */
192  isync
193
194  mfccr0  r28             /* set CCR0[24] = 1 */
195  ori     r28, r28, 0x0080
196  mtccr0  r28
197
198  /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
199  lis     r28, 0xEF40
200  addi    r28, r28, 0x0004
201  stw     r31, 0x0C(r28)  /* clear PMM0PCIHA */
202  lis     r29, 0xFFF8     /* open 512 kByte */
203  addi    r29, r29, 0x0001/* and enable this region */
204  stwbrx  r29, r0, r28    /* write PMM0MA */
205
206  lis     r28, 0xEEC0     /* address of PCIC0_CFGADDR */
207  addi    r29, r28, 4     /* add 4 to r29 -> PCIC0_CFGDATA */
208
209  lis     r31, 0x8000     /* set en bit bus 0 */
210  ori     r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
211  stwbrx  r31, r0, r28    /* write it */
212
213  lwbrx   r31, r0, r29    /* load XBCS register */
214  oris    r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
215  stwbrx  r31, r0, r29    /* write back XBCS register */
216
217  nop
218  nop
219  b     _start          /* normal start */
220#endif
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