source: SVN/rincon/u-boot/board/mpl/pip405/init.S @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 2 years ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 6.9 KB
Line 
1/*------------------------------------------------------------------------------+
2 *
3 *      This source code has been made available to you by IBM on an AS-IS
4 *      basis.  Anyone receiving this source is licensed under IBM
5 *      copyrights to use it in any way he or she deems fit, including
6 *      copying it, modifying it, compiling it, and redistributing it either
7 *      with or without modifications.  No license under IBM patents or
8 *      patent applications is to be implied by the copyright license.
9 *
10 *      Any user of this software should understand that IBM cannot provide
11 *      technical support for this software and will not be responsible for
12 *      any consequences resulting from the use of this software.
13 *
14 *      Any person who transfers this source code or any derivative work
15 *      must include the IBM copyright notice, this paragraph, and the
16 *      preceding two paragraphs in the transferred software.
17 *
18 *      COPYRIGHT   I B M   CORPORATION 1995
19 *      LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
20 *-------------------------------------------------------------------------------*/
21
22/*-----------------------------------------------------------------------------
23 * Function:     ext_bus_cntlr_init
24 * Description:  Initializes the External Bus Controller for the external
25 *              peripherals. IMPORTANT: For pass1 this code must run from
26 *              cache since you can not reliably change a peripheral banks
27 *              timing register (pbxap) while running code from that bank.
28 *              For ex., since we are running from ROM on bank 0, we can NOT
29 *              execute the code that modifies bank 0 timings from ROM, so
30 *              we run it from cache.
31 *      Bank 0 - Flash or Multi Purpose Socket
32 *      Bank 1 - Multi Purpose Socket or Flash
33 *      Bank 2 - not used
34 *      Bank 3 - not used
35 *      Bank 4 - not used
36 *      Bank 5 - not used
37 *      Bank 6 - used to switch on the 12V for the Multipurpose socket
38 *      Bank 7 - Config Register
39 *-----------------------------------------------------------------------------*/
40#include <ppc4xx.h>
41
42#define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
43
44#include <configs/PIP405.h>
45#include <ppc_asm.tmpl>
46#include <ppc_defs.h>
47
48#include <asm/cache.h>
49#include <asm/mmu.h>
50#include "pip405.h"
51
52  .globl ext_bus_cntlr_init
53 ext_bus_cntlr_init:
54  mflr   r4                      /* save link register */
55  mfdcr  r3,strap                /* get strapping reg */
56  andi.  r0, r3, PSR_ROM_LOC     /* mask out irrelevant bits */
57  bnelr                          /* jump back if PCI boot */
58
59  bl      ..getAddr
60..getAddr:
61  mflr    r3                      /* get address of ..getAddr */
62  mtlr    r4                      /* restore link register */
63  addi    r4,0,14                 /* set ctr to 14; used to prefetch */
64  mtctr   r4                      /* 14 cache lines to fit this function */
65                                   /* in cache (gives us 8x14=112 instrctns) */
66..ebcloop:
67  icbt    r0,r3                   /* prefetch cache line for addr in r3 */
68  addi    r3,r3,32                                                              /* move to next cache line */
69  bdnz    ..ebcloop               /* continue for 14 cache lines */
70
71   /*-------------------------------------------------------------------
72    * Delay to ensure all accesses to ROM are complete before changing
73    * bank 0 timings.
74    *------------------------------------------------------------------- */
75        addis   r3,0,0x0
76  ori     r3,r3,0xA000
77  mtctr   r3
78..spinlp:
79  bdnz    ..spinlp                /* spin loop */
80
81        /*-----------------------------------------------------------------------
82         * decide boot up mode
83         *----------------------------------------------------------------------- */
84        addi            r4,0,pb0cr
85        mtdcr           ebccfga,r4
86        mfdcr           r4,ebccfgd
87
88        andi.           r0, r4, 0x2000                  /* mask out irrelevant bits */
89        beq             0f                              /* jump if 8 bit bus width */
90
91        /* setup 16 bit things
92   *-----------------------------------------------------------------------
93   * Memory Bank 0 (16 Bit Flash) initialization
94   *---------------------------------------------------------------------- */
95
96        addi    r4,0,pb0ap
97        mtdcr   ebccfga,r4
98        addis   r4,0,(FLASH_AP_B)@h
99        ori     r4,r4,(FLASH_AP_B)@l
100        mtdcr   ebccfgd,r4
101
102        addi    r4,0,pb0cr
103        mtdcr   ebccfga,r4
104        /* BS=0x010(4MB),BU=0x3(R/W), */
105        addis   r4,0,(FLASH_CR_B)@h
106        ori     r4,r4,(FLASH_CR_B)@l
107        mtdcr   ebccfgd,r4
108        b                               1f
109
1100:
111        /* 8Bit boot mode: */
112        /*-----------------------------------------------------------------------
113        * Memory Bank 0 Multi Purpose Socket initialization
114        *----------------------------------------------------------------------- */
115        /* 0x7F8FFE80 slowest boot */
116        addi    r4,0,pb0ap
117        mtdcr   ebccfga,r4
118        addis   r4,0,(MPS_AP_B)@h
119        ori     r4,r4,(MPS_AP_B)@l
120        mtdcr   ebccfgd,r4
121
122        addi    r4,0,pb0cr
123        mtdcr   ebccfga,r4
124        /* BS=0x010(4MB),BU=0x3(R/W), */
125        addis   r4,0,(MPS_CR_B)@h
126        ori     r4,r4,(MPS_CR_B)@l
127        mtdcr   ebccfgd,r4
128
129
1301:
131  /*-----------------------------------------------------------------------
132   * Memory Bank 2-3-4-5-6 (not used) initialization
133   *-----------------------------------------------------------------------*/
134  addi    r4,0,pb1cr
135  mtdcr   ebccfga,r4
136  addis   r4,0,0x0000
137  ori     r4,r4,0x0000
138  mtdcr   ebccfgd,r4
139
140  addi    r4,0,pb2cr
141  mtdcr   ebccfga,r4
142  addis   r4,0,0x0000
143  ori     r4,r4,0x0000
144  mtdcr   ebccfgd,r4
145
146  addi    r4,0,pb3cr
147  mtdcr   ebccfga,r4
148  addis   r4,0,0x0000
149  ori     r4,r4,0x0000
150  mtdcr   ebccfgd,r4
151
152  addi    r4,0,pb4cr
153  mtdcr   ebccfga,r4
154  addis   r4,0,0x0000
155  ori     r4,r4,0x0000
156  mtdcr   ebccfgd,r4
157
158  addi    r4,0,pb5cr
159  mtdcr   ebccfga,r4
160  addis   r4,0,0x0000
161  ori     r4,r4,0x0000
162  mtdcr   ebccfgd,r4
163
164  addi    r4,0,pb6cr
165  mtdcr   ebccfga,r4
166  addis   r4,0,0x0000
167  ori     r4,r4,0x0000
168  mtdcr   ebccfgd,r4
169
170  addi    r4,0,pb7cr
171  mtdcr   ebccfga,r4
172  addis   r4,0,0x0000
173  ori     r4,r4,0x0000
174  mtdcr   ebccfgd,r4
175  nop                           /* pass2 DCR errata #8 */
176  blr
177
178#if defined(CONFIG_BOOT_PCI)
179    .section .bootpg,"ax"
180    .globl _start_pci
181/*******************************************
182 */
183
184_start_pci:
185  /* first handle errata #68 / PCI_18 */
186  iccci   r0, r0          /* invalidate I-cache */
187  lis     r31, 0
188  mticcr  r31             /* ICCR = 0 (all uncachable) */
189  isync
190
191  mfccr0  r28             /* set CCR0[24] = 1 */
192  ori     r28, r28, 0x0080
193  mtccr0  r28
194
195  /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
196  lis     r28, 0xEF40
197  addi    r28, r28, 0x0004
198  stw     r31, 0x0C(r28)  /* clear PMM0PCIHA */
199  lis     r29, 0xFFF8     /* open 512 kByte */
200  addi    r29, r29, 0x0001/* and enable this region */
201  stwbrx  r29, r0, r28    /* write PMM0MA */
202
203  lis     r28, 0xEEC0     /* address of PCIC0_CFGADDR */
204  addi    r29, r28, 4     /* add 4 to r29 -> PCIC0_CFGDATA */
205
206  lis     r31, 0x8000     /* set en bit bus 0 */
207  ori     r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
208  stwbrx  r31, r0, r28    /* write it */
209
210  lwbrx   r31, r0, r29    /* load XBCS register */
211  oris    r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
212  stwbrx  r31, r0, r29    /* write back XBCS register */
213
214  nop
215  nop
216  b     _start          /* normal start */
217#endif
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