source: SVN/rincon/u-boot/board/mpl/pip405/pip405.h @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 7.2 KB
Line 
1/*
2 * (C) Copyright 2001
3 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24 /****************************************************************************
25 * Global routines used for PIP405
26 *****************************************************************************/
27
28#ifndef __ASSEMBLY__
29
30extern int  mem_test(unsigned long start, unsigned long ramsize,int mode);
31
32void print_pip405_info(void);
33
34void user_led0(unsigned char on);
35void user_led1(unsigned char on);
36
37
38#define PLD_BASE_ADDRESS                CFG_ISA_IO_BASE_ADDRESS + 0x800
39#define PLD_PART_REG                    PLD_BASE_ADDRESS + 0
40#define PLD_VERS_REG                    PLD_BASE_ADDRESS + 1
41#define PLD_BOARD_CFG_REG               PLD_BASE_ADDRESS + 2
42#define PLD_LED_USER_REG                PLD_BASE_ADDRESS + 3
43#define PLD_SYS_MAN_REG                 PLD_BASE_ADDRESS + 4
44#define PLD_FLASH_COM_REG               PLD_BASE_ADDRESS + 5
45#define PLD_CAN_REG                     PLD_BASE_ADDRESS + 6
46#define PLD_SER_PWR_REG                 PLD_BASE_ADDRESS + 7
47#define PLD_COM_PWR_REG                 PLD_BASE_ADDRESS + 8
48#define PLD_NIC_VGA_REG                 PLD_BASE_ADDRESS + 9
49#define PLD_SCSI_RST_REG                PLD_BASE_ADDRESS + 0xA
50
51#define PIIX4_VENDOR_ID                 0x8086
52#define PIIX4_IDE_DEV_ID                0x7111
53
54#endif
55
56/* timings */
57
58/* CS Config register (CS7) */
59#define CONFIG_PORT_BME 0       /* Burst disable */
60#define CONFIG_PORT_TWE 255     /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
61#define CONFIG_PORT_CSN 1       /* Chipselect is driven inactive for 1 Cycle BTW transfers */
62#define CONFIG_PORT_OEN 1       /* Cycles from CS low to OE low   */
63#define CONFIG_PORT_WBN 1       /* Cycles from CS low to WE low   */
64#define CONFIG_PORT_WBF 1       /* Cycles from WE high to CS high */
65#define CONFIG_PORT_TH  2       /* Number of hold cycles after transfer */
66#define CONFIG_PORT_RE  0       /* Ready disabled */
67#define CONFIG_PORT_SOR 1       /* Sample on Ready disabled */
68#define CONFIG_PORT_BEM 0       /* Byte Write only active on Write cycles */
69#define CONFIG_PORT_PEN 0       /* Parity disable */
70#define CONFIG_PORT_AP  ((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \
71                                (CONFIG_PORT_WBF << 12) + (CONFIG_PORT_TH << 9) + (CONFIG_PORT_RE << 8) + (CONFIG_PORT_SOR << 7) + (CONFIG_PORT_BEM << 6) + (CONFIG_PORT_PEN << 5))
72
73/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
74#define CONFIG_PORT_BS  0       /* 1 MByte */
75/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
76#define CONFIG_PORT_BU  3       /* R/W */
77/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
78#define CONFIG_PORT_BW  0       /* 16Bit */
79#define CONFIG_PORT_CR  ((CONFIG_PORT_ADDR & 0xfff00000) + (CONFIG_PORT_BS << 17) + (CONFIG_PORT_BU << 15) + (CONFIG_PORT_BW << 13))
80
81/* Flash CS0 or CS 1 */
82/* 0x7F8FFE80 slowest timing at all... */
83#define FLASH_BME_B     1       /* Burst enable */
84#define FLASH_FWT_B     0x6     /* 6 * 30ns 210ns First Wait Access */
85#define FLASH_BWT_B     0x6     /* 6 * 30ns 210ns Burst Wait Access */
86#define FLASH_BME       0       /* Burst disable */
87#define FLASH_TWE       0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
88#define FLASH_CSN       0       /* Chipselect is driven inactive for 1 Cycle BTW transfers */
89#define FLASH_OEN       1       /* Cycles from CS low to OE low   */
90#define FLASH_WBN       1       /* Cycles from CS low to WE low   */
91#define FLASH_WBF       1       /* Cycles from WE high to CS high */
92#define FLASH_TH        2       /* Number of hold cycles after transfer */
93#define FLASH_RE        0       /* Ready disabled */
94#define FLASH_SOR       1       /* Sample on Ready disabled */
95#define FLASH_BEM       0       /* Byte Write only active on Write cycles */
96#define FLASH_PEN       0       /* Parity disable */
97/* Access Parameter Register for non Boot */
98#define FLASH_AP        ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
99                                (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
100/* Access Parameter Register for Boot */
101#define FLASH_AP_B      ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
102                                (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
103
104/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
105#define FLASH_BS        FLASH_SIZE_PRELIM       /* 4 MByte */
106/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
107#define FLASH_BU        3       /* R/W */
108/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
109#define FLASH_BW        1       /* 16Bit */
110/* CR register for Boot */
111#define FLASH_CR_B      ((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
112/* CR register for non Boot */
113#define FLASH_CR        ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
114
115/* MPS CS1 or CS0 */
116/* Boot CS: */
117#define MPS_BME_B       1       /* Burst enable */
118#define MPS_FWT_B       0x6/* 6 * 30ns 210ns First Wait Access */
119#define MPS_BWT_B       0x6     /* 6 * 30ns 210ns Burst Wait Access */
120#define MPS_BME         0       /* Burst disable */
121#define MPS_TWE         0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
122#define MPS_CSN         0       /* Chipselect is driven inactive for 1 Cycle BTW transfers */
123#define MPS_OEN         1       /* Cycles from CS low to OE low   */
124#define MPS_WBN         1       /* Cycles from CS low to WE low   */
125#define MPS_WBF         1       /* Cycles from WE high to CS high */
126#define MPS_TH          2       /* Number of hold cycles after transfer */
127#define MPS_RE          0       /* Ready disabled */
128#define MPS_SOR         1       /* Sample on Ready disabled */
129#define MPS_BEM         0       /* Byte Write only active on Write cycles */
130#define MPS_PEN         0       /* Parity disable */
131/* Access Parameter Register for non Boot */
132#define MPS_AP          ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
133                                (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
134/* Access Parameter Register for Boot */
135#define MPS_AP_B        ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
136                                (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
137
138/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
139#define MPS_BS          2       /* 4 MByte */
140#define MPS_BS_B                FLASH_SIZE_PRELIM       /* 1 MByte */
141/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
142#define MPS_BU          3       /* R/W */
143/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
144#define MPS_BW          0       /* 8Bit */
145/* CR register for Boot */
146#define MPS_CR_B        ((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
147/* CR register for non Boot */
148#define MPS_CR          ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
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