source: SVN/rincon/u-boot/board/mx1ads/mx1ads.c @ 55

Last change on this file since 55 was 55, checked in by Tim Harvey, 22 months ago

rincon: added latest u-boot source

restored form server backup

Signed-off-by: Tim Harvey <tharvey@…>

File size: 3.8 KB
Line 
1/*
2 * board/mx1ads/mx1ads.c
3 *
4 * (c) Copyright 2004
5 * Techware Information Technology, Inc.
6 * http://www.techware.com.tw/
7 *
8 * Ming-Len Wu <minglen_wu@techware.com.tw>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27/*#include <mc9328.h>*/
28#include <asm/arch/imx-regs.h>
29
30DECLARE_GLOBAL_DATA_PTR;
31
32#define FCLK_SPEED 1
33
34#if FCLK_SPEED==0               /* Fout = 203MHz, Fin = 12MHz for Audio */
35#define M_MDIV  0xC3
36#define M_PDIV  0x4
37#define M_SDIV  0x1
38#elif FCLK_SPEED==1             /* Fout = 202.8MHz */
39#define M_MDIV  0xA1
40#define M_PDIV  0x3
41#define M_SDIV  0x1
42#endif
43
44#define USB_CLOCK 1
45
46#if USB_CLOCK==0
47#define U_M_MDIV        0xA1
48#define U_M_PDIV        0x3
49#define U_M_SDIV        0x1
50#elif USB_CLOCK==1
51#define U_M_MDIV        0x48
52#define U_M_PDIV        0x3
53#define U_M_SDIV        0x2
54#endif
55
56#if 0
57
58static inline void delay (unsigned long loops)
59{
60        __asm__ volatile ("1:\n"
61                          "subs %0, %1, #1\n"
62                          "bne 1b":"=r" (loops):"0" (loops));
63}
64
65#endif
66
67/*
68 * Miscellaneous platform dependent initialisations
69 */
70
71void SetAsynchMode (void)
72{
73        __asm__ ("mrc p15,0,r0,c1,c0,0 \n"
74                 "mov r2, #0xC0000000 \n"
75                 "orr r0,r2,r0 \n" "mcr p15,0,r0,c1,c0,0 \n");
76}
77
78static u32 mc9328sid;
79
80int board_init (void)
81{
82        volatile unsigned int tmp;
83
84        mc9328sid = SIDR;
85
86        GPCR = 0x000003AB;      /* I/O pad driving strength     */
87
88        /*      MX1_CS1U        = 0x00000A00;   */ /* SRAM initialization          */
89/*      MX1_CS1L        = 0x11110601;   */
90
91        MPCTL0 = 0x04632410;    /* setting for 150 MHz MCU PLL CLK      */
92
93/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
94 * BCLK divider to 2 (i.e. BCLK to 48 MHz)
95 */
96        CSCR = 0xAF000403;
97
98        CSCR |= 0x00200000;     /* Trigger the restart bit(bit 21)      */
99        CSCR &= 0xFFFF7FFF;     /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
100
101/* setup cs4 for cs8900 ethernet */
102
103        CS4U = 0x00000F00;      /* Initialize CS4 for CS8900 ethernet   */
104        CS4L = 0x00001501;
105
106        GIUS (0) &= 0xFF3FFFFF;
107        GPR (0) &= 0xFF3FFFFF;
108
109        tmp = *(unsigned int *) (0x1500000C);
110        tmp = *(unsigned int *) (0x1500000C);
111
112        SetAsynchMode ();
113
114        gd->bd->bi_arch_number = MACH_TYPE_MX1ADS;
115
116        gd->bd->bi_boot_params = 0x08000100;    /* adress of boot parameters    */
117
118        icache_enable ();
119        dcache_enable ();
120
121/* set PERCLKs                          */
122        PCDR = 0x00000055;      /* set PERCLKS                          */
123
124/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
125 * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
126 * all sources selected as normal interrupt
127 */
128
129/*      MX1_INTTYPEH = 0;
130        MX1_INTTYPEL = 0;
131*/
132        return 0;
133}
134
135int board_late_init (void)
136{
137
138        setenv ("stdout", "serial");
139        setenv ("stderr", "serial");
140
141        switch (mc9328sid) {
142        case 0x0005901d:
143                printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",
144                        mc9328sid);
145                break;
146        case 0x04d4c01d:
147                printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",
148                        mc9328sid);
149                break;
150        case 0x00d4c01d:
151                printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",
152                        mc9328sid);
153                break;
154
155        default:
156                printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",
157                        mc9328sid);
158                break;
159        }
160        return 0;
161}
162
163int dram_init (void)
164{
165        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
166        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
167
168        return 0;
169}
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