1 | /* |
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2 | *(C) Copyright 2005-2008 Netstal Maschinen AG |
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3 | * Niklaus Giger (Niklaus.Giger@netstal.com) |
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4 | * |
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5 | * This source code is free software; you can redistribute it |
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6 | * and/or modify it in source code form under the terms of the GNU |
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7 | * General Public License as published by the Free Software |
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8 | * Foundation; either version 2 of the License, or (at your option) |
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9 | * any later version. |
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10 | * |
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11 | * This program is distributed in the hope that it will be useful, |
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12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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14 | * GNU General Public License for more details. |
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15 | * |
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16 | * You should have received a copy of the GNU General Public License |
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17 | * along with this program; if not, write to the Free Software |
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18 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA |
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19 | */ |
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20 | |
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21 | #include <common.h> |
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22 | #include <ppc4xx.h> |
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23 | #include <asm/processor.h> |
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24 | #include "nm.h" |
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25 | |
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26 | #if defined(DEBUG) |
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27 | void show_sdram_registers(void) |
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28 | { |
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29 | u32 value; |
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30 | |
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31 | printf("SDRAM Controller Registers --\n"); |
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32 | mfsdram(mem_mcopt1, value); |
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33 | printf(" SDRAM0_CFG : 0x%08x\n", value); |
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34 | mfsdram(mem_status, value); |
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35 | printf(" SDRAM0_STATUS: 0x%08x\n", value); |
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36 | mfsdram(mem_mb0cf, value); |
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37 | printf(" SDRAM0_B0CR : 0x%08x\n", value); |
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38 | mfsdram(mem_mb1cf, value); |
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39 | printf(" SDRAM0_B1CR : 0x%08x\n", value); |
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40 | mfsdram(mem_sdtr1, value); |
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41 | printf(" SDRAM0_TR : 0x%08x\n", value); |
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42 | mfsdram(mem_rtr, value); |
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43 | printf(" SDRAM0_RTR : 0x%08x\n", value); |
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44 | } |
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45 | #endif |
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46 | |
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47 | long int init_ppc405_sdram(unsigned int dram_size) |
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48 | { |
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49 | #ifdef DEBUG |
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50 | printf(__FUNCTION__); |
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51 | #endif |
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52 | /* disable memory controller */ |
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53 | mtsdram(mem_mcopt1, 0x00000000); |
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54 | |
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55 | udelay (500); |
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56 | |
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57 | /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */ |
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58 | mtsdram(mem_besra, 0xffffffff); |
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59 | |
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60 | /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */ |
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61 | mtsdram(mem_besrb, 0xffffffff); |
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62 | |
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63 | /* Clear SDRAM0_ECCCFG (disable ECC) */ |
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64 | mtsdram(mem_ecccf, 0x00000000); |
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65 | |
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66 | /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */ |
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67 | mtsdram(mem_eccerr, 0xffffffff); |
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68 | |
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69 | /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 |
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70 | */ |
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71 | mtsdram(mem_sdtr1, 0x008a4015); |
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72 | |
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73 | /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 |
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74 | * and refresh timer |
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75 | */ |
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76 | switch (dram_size >> 20) { |
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77 | case 32: |
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78 | mtsdram(mem_mb0cf, 0x00062001); |
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79 | mtsdram(mem_rtr, 0x07F00000); |
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80 | break; |
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81 | case 64: |
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82 | mtsdram(mem_mb0cf, 0x00084001); |
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83 | mtsdram(mem_rtr, 0x04100000); |
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84 | break; |
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85 | case 128: |
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86 | mtsdram(mem_mb0cf, 0x000A4001); |
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87 | mtsdram(mem_rtr, 0x04100000); |
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88 | break; |
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89 | default: |
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90 | printf("Invalid memory size of %d MB given\n", dram_size >> 20); |
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91 | } |
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92 | |
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93 | /* Power management idle timer set to the default. */ |
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94 | mtsdram(mem_pmit, 0x07c00000); |
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95 | |
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96 | udelay (500); |
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97 | |
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98 | /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */ |
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99 | mtsdram(mem_mcopt1, 0x90800000); |
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100 | |
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101 | #ifdef DEBUG |
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102 | printf("%s: done\n", __FUNCTION__); |
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103 | #endif |
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104 | return dram_size; |
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105 | } |
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